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olivier.gi |
Welcome to Xilinx CORE Generator.
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Help system initialized.
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The IP Catalog has been reloaded.
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Wrote CGP file for project 'coregen'.
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Customize and GenerateINFO:sim:172 - Generating IP...
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WARNING:sim:100 - The Simulation File Type is not valid for this
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core. Overriding with File Type .
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Applying current project options...
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Finished applying current project options.
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Customizing IP...
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Release 14.2 - Xilinx CORE Generator IP GUI Launcher P.28xd (lin64)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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terminate called after throwing an instance of 'Port_ThrException::Exception'
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Finished Customizing.
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Generating IP...
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WARNING:sim:100 - The Simulation File Type is not valid for this
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core. Overriding with File Type .
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Configuring files for chipscope_icon root...
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Gathering HDL files for chipscope_icon root...
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Creating XST project for chipscope_icon...
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Creating XST script file for chipscope_icon...
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Creating XST instantiation file for chipscope_icon...
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Running XST for chipscope_icon...
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XST: HDL Parsing
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XST: HDL Elaboration
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XST: HDL Synthesis
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XST: Advanced HDL Synthesis
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XST: Low Level Synthesis
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XST: Design Summary
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Not generating VHDL wrapper
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Generating Verilog wrapper
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Skipping VHDL instantiation template for chipscope_icon...
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Creating ISE instantiation template for chipscope_icon...
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Finished Generation.
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Generating IP instantiation template...
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating metadata file...
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Generating ISE project...
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XCO file found: chipscope_icon.xco
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XMDF file found: chipscope_icon_xmdf.tcl
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen_chipscope/tmp/_cg/chipscope_icon.asy -view all -origin_type
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imported
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen_chipscope/tmp/_cg/chipscope_icon.ngc -view all -origin_type created
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Checking file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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rilog/coregen_chipscope/tmp/_cg/chipscope_icon.ngc" for project device match ...
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File
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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rilog/coregen_chipscope/tmp/_cg/chipscope_icon.ngc" device information matches
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project device.
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen_chipscope/tmp/_cg/chipscope_icon.v -view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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/verilog/coregen_chipscope/tmp/_cg/chipscope_icon.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen_chipscope/tmp/_cg/chipscope_icon.veo -view all -origin_type
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imported
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/chipscope_icon"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Customize and GenerateINFO:sim:172 - Generating IP...
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WARNING:sim:100 - The Simulation File Type is not valid for this
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core. Overriding with File Type .
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Applying current project options...
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Finished applying current project options.
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Customizing IP...
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Release 14.2 - Xilinx CORE Generator IP GUI Launcher P.28xd (lin64)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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terminate called after throwing an instance of 'Port_ThrException::Exception'
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Finished Customizing.
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Generating IP...
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WARNING:sim:100 - The Simulation File Type is not valid for this
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core. Overriding with File Type .
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Configuring files for chipscope_ila root...
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Gathering HDL files for chipscope_ila root...
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Creating XST project for chipscope_ila...
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Creating XST script file for chipscope_ila...
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Creating XST instantiation file for chipscope_ila...
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Running XST for chipscope_ila...
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XST: HDL Parsing
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XST: HDL Elaboration
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XST: HDL Synthesis
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XST: Advanced HDL Synthesis
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XST: Low Level Synthesis
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XST: Design Summary
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Not generating VHDL wrapper
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Generating Verilog wrapper
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Skipping VHDL instantiation template for chipscope_ila...
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Creating ISE instantiation template for chipscope_ila...
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Finished Generation.
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Generating IP instantiation template...
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating metadata file...
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Generating ISE project...
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XCO file found: chipscope_ila.xco
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XMDF file found: chipscope_ila_xmdf.tcl
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen_chipscope/tmp/_cg/chipscope_ila.asy -view all -origin_type imported
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen_chipscope/tmp/_cg/chipscope_ila.ngc -view all -origin_type created
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Checking file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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rilog/coregen_chipscope/tmp/_cg/chipscope_ila.ngc" for project device match ...
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File
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ve
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rilog/coregen_chipscope/tmp/_cg/chipscope_ila.ngc" device information matches
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project device.
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen_chipscope/tmp/_cg/chipscope_ila.v -view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl
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/verilog/coregen_chipscope/tmp/_cg/chipscope_ila.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/ver
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ilog/coregen_chipscope/tmp/_cg/chipscope_ila.veo -view all -origin_type imported
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/chipscope_ila"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Saved CGP file for project 'coregen'.
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Closed project file.
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