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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [synthesis/] [xilinx/] [scripts/] [memory.bmm] - Blame information for rev 167

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Line No. Rev Author Line
1 167 olivier.gi 
ADDRESS_SPACE blockrom COMBINED [0x0000:0x3fff]
2 157 olivier.gi 
 
3 167 olivier.gi 
  ADDRESS_RANGE RAMB16 /* 0x0000 - 0x0FFF */
4 
    BUS_BLOCK
5 
        ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [15:8]  LOC = X0Y18;
6 
        ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  [7:0]  LOC = X0Y10;
7 
    END_BUS_BLOCK;
8 
  END_ADDRESS_RANGE;
9 157 olivier.gi 
 
10 167 olivier.gi 
  ADDRESS_RANGE RAMB16 /* 0x1000 - 0x1FFF */
11 
    BUS_BLOCK
12 
        ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [15:8]  LOC = X0Y24;
13 
        ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  [7:0]  LOC = X0Y16;
14 
    END_BUS_BLOCK;
15 
  END_ADDRESS_RANGE;
16 157 olivier.gi 
 
17 167 olivier.gi 
  ADDRESS_RANGE RAMB16 /* 0x2000 - 0x2FFF */
18 
    BUS_BLOCK
19 
        ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [15:8]  LOC = X0Y22;
20 
        ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  [7:0]  LOC = X0Y14;
21 
    END_BUS_BLOCK;
22 
  END_ADDRESS_RANGE;
23 157 olivier.gi 
 
24 167 olivier.gi 
  ADDRESS_RANGE RAMB16 /* 0x3000 - 0x3FFF */
25 
    BUS_BLOCK
26 
        ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram [15:8]  LOC = X0Y20;
27 
        ram_16x8k_dp_pmem_shared/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  [7:0]  LOC = X0Y12;
28 
    END_BUS_BLOCK;
29 
  END_ADDRESS_RANGE;
30 
 
31 157 olivier.gi 
END_ADDRESS_SPACE;

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