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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [registers.v] - Blame information for rev 2

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1 2 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: registers.v
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//
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// *Module Description:
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//                      openMSP430 testbench
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// CPU registers
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//======================
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wire       [15:0] r0    = dut.openMSP430_0.execution_unit_0.register_file_0.r0;
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wire       [15:0] r1    = dut.openMSP430_0.execution_unit_0.register_file_0.r1;
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wire       [15:0] r2    = dut.openMSP430_0.execution_unit_0.register_file_0.r2;
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wire       [15:0] r3    = dut.openMSP430_0.execution_unit_0.register_file_0.r3;
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wire       [15:0] r4    = dut.openMSP430_0.execution_unit_0.register_file_0.r4;
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wire       [15:0] r5    = dut.openMSP430_0.execution_unit_0.register_file_0.r5;
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wire       [15:0] r6    = dut.openMSP430_0.execution_unit_0.register_file_0.r6;
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wire       [15:0] r7    = dut.openMSP430_0.execution_unit_0.register_file_0.r7;
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wire       [15:0] r8    = dut.openMSP430_0.execution_unit_0.register_file_0.r8;
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wire       [15:0] r9    = dut.openMSP430_0.execution_unit_0.register_file_0.r9;
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wire       [15:0] r10   = dut.openMSP430_0.execution_unit_0.register_file_0.r10;
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wire       [15:0] r11   = dut.openMSP430_0.execution_unit_0.register_file_0.r11;
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wire       [15:0] r12   = dut.openMSP430_0.execution_unit_0.register_file_0.r12;
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wire       [15:0] r13   = dut.openMSP430_0.execution_unit_0.register_file_0.r13;
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wire       [15:0] r14   = dut.openMSP430_0.execution_unit_0.register_file_0.r14;
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wire       [15:0] r15   = dut.openMSP430_0.execution_unit_0.register_file_0.r15;
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// RAM cells
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//======================
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wire       [15:0] mem200 = {dut.ram_8x512_hi_0.inst.mem[0],  dut.ram_8x512_lo_0.inst.mem[0]};
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wire       [15:0] mem202 = {dut.ram_8x512_hi_0.inst.mem[1],  dut.ram_8x512_lo_0.inst.mem[1]};
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wire       [15:0] mem204 = {dut.ram_8x512_hi_0.inst.mem[2],  dut.ram_8x512_lo_0.inst.mem[2]};
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wire       [15:0] mem206 = {dut.ram_8x512_hi_0.inst.mem[3],  dut.ram_8x512_lo_0.inst.mem[3]};
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wire       [15:0] mem208 = {dut.ram_8x512_hi_0.inst.mem[4],  dut.ram_8x512_lo_0.inst.mem[4]};
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wire       [15:0] mem20A = {dut.ram_8x512_hi_0.inst.mem[5],  dut.ram_8x512_lo_0.inst.mem[5]};
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wire       [15:0] mem20C = {dut.ram_8x512_hi_0.inst.mem[6],  dut.ram_8x512_lo_0.inst.mem[6]};
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wire       [15:0] mem20E = {dut.ram_8x512_hi_0.inst.mem[7],  dut.ram_8x512_lo_0.inst.mem[7]};
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wire       [15:0] mem210 = {dut.ram_8x512_hi_0.inst.mem[8],  dut.ram_8x512_lo_0.inst.mem[8]};
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wire       [15:0] mem212 = {dut.ram_8x512_hi_0.inst.mem[9],  dut.ram_8x512_lo_0.inst.mem[9]};
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wire       [15:0] mem214 = {dut.ram_8x512_hi_0.inst.mem[10], dut.ram_8x512_lo_0.inst.mem[10]};
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wire       [15:0] mem216 = {dut.ram_8x512_hi_0.inst.mem[11], dut.ram_8x512_lo_0.inst.mem[11]};
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wire       [15:0] mem218 = {dut.ram_8x512_hi_0.inst.mem[12], dut.ram_8x512_lo_0.inst.mem[12]};
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wire       [15:0] mem21A = {dut.ram_8x512_hi_0.inst.mem[13], dut.ram_8x512_lo_0.inst.mem[13]};
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wire       [15:0] mem21C = {dut.ram_8x512_hi_0.inst.mem[14], dut.ram_8x512_lo_0.inst.mem[14]};
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wire       [15:0] mem21E = {dut.ram_8x512_hi_0.inst.mem[15], dut.ram_8x512_lo_0.inst.mem[15]};
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wire       [15:0] mem220 = {dut.ram_8x512_hi_0.inst.mem[16], dut.ram_8x512_lo_0.inst.mem[16]};
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wire       [15:0] mem222 = {dut.ram_8x512_hi_0.inst.mem[17], dut.ram_8x512_lo_0.inst.mem[17]};
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wire       [15:0] mem224 = {dut.ram_8x512_hi_0.inst.mem[18], dut.ram_8x512_lo_0.inst.mem[18]};
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wire       [15:0] mem226 = {dut.ram_8x512_hi_0.inst.mem[19], dut.ram_8x512_lo_0.inst.mem[19]};
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wire       [15:0] mem228 = {dut.ram_8x512_hi_0.inst.mem[20], dut.ram_8x512_lo_0.inst.mem[20]};
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wire       [15:0] mem22A = {dut.ram_8x512_hi_0.inst.mem[21], dut.ram_8x512_lo_0.inst.mem[21]};
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wire       [15:0] mem22C = {dut.ram_8x512_hi_0.inst.mem[22], dut.ram_8x512_lo_0.inst.mem[22]};
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wire       [15:0] mem22E = {dut.ram_8x512_hi_0.inst.mem[23], dut.ram_8x512_lo_0.inst.mem[23]};
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wire       [15:0] mem230 = {dut.ram_8x512_hi_0.inst.mem[24], dut.ram_8x512_lo_0.inst.mem[24]};
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wire       [15:0] mem232 = {dut.ram_8x512_hi_0.inst.mem[25], dut.ram_8x512_lo_0.inst.mem[25]};
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wire       [15:0] mem234 = {dut.ram_8x512_hi_0.inst.mem[26], dut.ram_8x512_lo_0.inst.mem[26]};
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wire       [15:0] mem236 = {dut.ram_8x512_hi_0.inst.mem[27], dut.ram_8x512_lo_0.inst.mem[27]};
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wire       [15:0] mem238 = {dut.ram_8x512_hi_0.inst.mem[28], dut.ram_8x512_lo_0.inst.mem[28]};
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wire       [15:0] mem23A = {dut.ram_8x512_hi_0.inst.mem[29], dut.ram_8x512_lo_0.inst.mem[29]};
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wire       [15:0] mem23C = {dut.ram_8x512_hi_0.inst.mem[30], dut.ram_8x512_lo_0.inst.mem[30]};
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wire       [15:0] mem23E = {dut.ram_8x512_hi_0.inst.mem[31], dut.ram_8x512_lo_0.inst.mem[31]};
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wire       [15:0] mem240 = {dut.ram_8x512_hi_0.inst.mem[32], dut.ram_8x512_lo_0.inst.mem[32]};
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wire       [15:0] mem242 = {dut.ram_8x512_hi_0.inst.mem[33], dut.ram_8x512_lo_0.inst.mem[33]};
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wire       [15:0] mem244 = {dut.ram_8x512_hi_0.inst.mem[34], dut.ram_8x512_lo_0.inst.mem[34]};
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wire       [15:0] mem246 = {dut.ram_8x512_hi_0.inst.mem[35], dut.ram_8x512_lo_0.inst.mem[35]};
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wire       [15:0] mem248 = {dut.ram_8x512_hi_0.inst.mem[36], dut.ram_8x512_lo_0.inst.mem[36]};
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wire       [15:0] mem24A = {dut.ram_8x512_hi_0.inst.mem[37], dut.ram_8x512_lo_0.inst.mem[37]};
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wire       [15:0] mem24C = {dut.ram_8x512_hi_0.inst.mem[38], dut.ram_8x512_lo_0.inst.mem[38]};
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wire       [15:0] mem24E = {dut.ram_8x512_hi_0.inst.mem[39], dut.ram_8x512_lo_0.inst.mem[39]};
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wire       [15:0] mem250 = {dut.ram_8x512_hi_0.inst.mem[40], dut.ram_8x512_lo_0.inst.mem[40]};
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wire       [15:0] mem252 = {dut.ram_8x512_hi_0.inst.mem[41], dut.ram_8x512_lo_0.inst.mem[41]};
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wire       [15:0] mem254 = {dut.ram_8x512_hi_0.inst.mem[42], dut.ram_8x512_lo_0.inst.mem[42]};
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wire       [15:0] mem256 = {dut.ram_8x512_hi_0.inst.mem[43], dut.ram_8x512_lo_0.inst.mem[43]};
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wire       [15:0] mem258 = {dut.ram_8x512_hi_0.inst.mem[44], dut.ram_8x512_lo_0.inst.mem[44]};
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wire       [15:0] mem25A = {dut.ram_8x512_hi_0.inst.mem[45], dut.ram_8x512_lo_0.inst.mem[45]};
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wire       [15:0] mem25C = {dut.ram_8x512_hi_0.inst.mem[46], dut.ram_8x512_lo_0.inst.mem[46]};
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wire       [15:0] mem25E = {dut.ram_8x512_hi_0.inst.mem[47], dut.ram_8x512_lo_0.inst.mem[47]};
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wire       [15:0] mem260 = {dut.ram_8x512_hi_0.inst.mem[48], dut.ram_8x512_lo_0.inst.mem[48]};
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wire       [15:0] mem262 = {dut.ram_8x512_hi_0.inst.mem[49], dut.ram_8x512_lo_0.inst.mem[49]};
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wire       [15:0] mem264 = {dut.ram_8x512_hi_0.inst.mem[50], dut.ram_8x512_lo_0.inst.mem[50]};
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wire       [15:0] mem266 = {dut.ram_8x512_hi_0.inst.mem[51], dut.ram_8x512_lo_0.inst.mem[51]};
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wire       [15:0] mem268 = {dut.ram_8x512_hi_0.inst.mem[52], dut.ram_8x512_lo_0.inst.mem[52]};
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wire       [15:0] mem26A = {dut.ram_8x512_hi_0.inst.mem[53], dut.ram_8x512_lo_0.inst.mem[53]};
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wire       [15:0] mem26C = {dut.ram_8x512_hi_0.inst.mem[54], dut.ram_8x512_lo_0.inst.mem[54]};
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wire       [15:0] mem26E = {dut.ram_8x512_hi_0.inst.mem[55], dut.ram_8x512_lo_0.inst.mem[55]};
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wire       [15:0] mem270 = {dut.ram_8x512_hi_0.inst.mem[56], dut.ram_8x512_lo_0.inst.mem[56]};
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wire       [15:0] mem272 = {dut.ram_8x512_hi_0.inst.mem[57], dut.ram_8x512_lo_0.inst.mem[57]};
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wire       [15:0] mem274 = {dut.ram_8x512_hi_0.inst.mem[58], dut.ram_8x512_lo_0.inst.mem[58]};
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wire       [15:0] mem276 = {dut.ram_8x512_hi_0.inst.mem[59], dut.ram_8x512_lo_0.inst.mem[59]};
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wire       [15:0] mem278 = {dut.ram_8x512_hi_0.inst.mem[60], dut.ram_8x512_lo_0.inst.mem[60]};
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wire       [15:0] mem27A = {dut.ram_8x512_hi_0.inst.mem[61], dut.ram_8x512_lo_0.inst.mem[61]};
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wire       [15:0] mem27C = {dut.ram_8x512_hi_0.inst.mem[62], dut.ram_8x512_lo_0.inst.mem[62]};
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wire       [15:0] mem27E = {dut.ram_8x512_hi_0.inst.mem[63], dut.ram_8x512_lo_0.inst.mem[63]};
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wire       [15:0] mem280 = {dut.ram_8x512_hi_0.inst.mem[64], dut.ram_8x512_lo_0.inst.mem[64]};
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// ROM cells
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//======================
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reg   [15:0] rom_mem [2047:0];
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// Interrupt vectors
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wire  [15:0] irq_vect_15 = rom_mem[(1<<(`ROM_MSB+1))-1];  // RESET Vector
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wire  [15:0] irq_vect_14 = rom_mem[(1<<(`ROM_MSB+1))-2];  // NMI
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wire  [15:0] irq_vect_13 = rom_mem[(1<<(`ROM_MSB+1))-3];  // IRQ 13
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wire  [15:0] irq_vect_12 = rom_mem[(1<<(`ROM_MSB+1))-4];  // IRQ 12
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wire  [15:0] irq_vect_11 = rom_mem[(1<<(`ROM_MSB+1))-5];  // IRQ 11
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wire  [15:0] irq_vect_10 = rom_mem[(1<<(`ROM_MSB+1))-6];  // IRQ 10
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wire  [15:0] irq_vect_09 = rom_mem[(1<<(`ROM_MSB+1))-7];  // IRQ  9
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wire  [15:0] irq_vect_08 = rom_mem[(1<<(`ROM_MSB+1))-8];  // IRQ  8
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wire  [15:0] irq_vect_07 = rom_mem[(1<<(`ROM_MSB+1))-9];  // IRQ  7
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wire  [15:0] irq_vect_06 = rom_mem[(1<<(`ROM_MSB+1))-10]; // IRQ  6
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wire  [15:0] irq_vect_05 = rom_mem[(1<<(`ROM_MSB+1))-11]; // IRQ  5
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wire  [15:0] irq_vect_04 = rom_mem[(1<<(`ROM_MSB+1))-12]; // IRQ  4
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wire  [15:0] irq_vect_03 = rom_mem[(1<<(`ROM_MSB+1))-13]; // IRQ  3
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wire  [15:0] irq_vect_02 = rom_mem[(1<<(`ROM_MSB+1))-14]; // IRQ  2
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wire  [15:0] irq_vect_01 = rom_mem[(1<<(`ROM_MSB+1))-15]; // IRQ  1
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wire  [15:0] irq_vect_00 = rom_mem[(1<<(`ROM_MSB+1))-16]; // IRQ  0
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// CPU internals
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//======================
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wire mclk = dut.openMSP430_0.mclk;
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wire puc  = dut.openMSP430_0.puc;

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