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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 111

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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: tb_openMSP430_fpga.v
// 
// *Module Description:
//                      openMSP430 FPGA testbench
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 111 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
 
module  tb_openMSP430_fpga;
 
//
// Wire & Register definition
//------------------------------
 
// Clock & Reset
reg               CLK_50MHz;
reg               RESET;
 
// Slide Switches
reg               SW7;
reg               SW6;
reg               SW5;
reg               SW4;
reg               SW3;
reg               SW2;
reg               SW1;
reg               SW0;
 
// Push Button Switches
reg               BTN2;
reg               BTN1;
reg               BTN0;
 
// LEDs
wire              LED7;
wire              LED6;
wire              LED5;
wire              LED4;
wire              LED3;
wire              LED2;
wire              LED1;
wire              LED0;
 
// Four-Sigit, Seven-Segment LED Display
wire              SEG_A;
wire              SEG_B;
wire              SEG_C;
wire              SEG_D;
wire              SEG_E;
wire              SEG_F;
wire              SEG_G;
wire              SEG_DP;
wire              SEG_AN0;
wire              SEG_AN1;
wire              SEG_AN2;
wire              SEG_AN3;
 
// UART
reg               UART_RXD;
wire              UART_TXD;
 
// Core debug signals
wire   [8*32-1:0] i_state;
wire   [8*32-1:0] e_state;
wire       [31:0] inst_cycle;
wire   [8*32-1:0] inst_full;
wire       [31:0] inst_number;
wire       [15:0] inst_pc;
wire   [8*32-1:0] inst_short;
 
// Testbench variables
integer           i;
integer           error;
reg               stimulus_done;
 
 
//
// Include files
//------------------------------
 
// CPU & Memory registers
`include "registers.v"
 
// Verilog stimulus
`include "stimulus.v"
 
//
// Initialize Program Memory
//------------------------------
 
initial
   begin
      // Read memory file
      #10 $readmemh("./pmem.mem", pmem);
 
      // Update Xilinx memory banks
      for (i=0; i<2048; i=i+1)
        begin
           dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
           dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
        end
  end
 
//
// Generate Clock & Reset
//------------------------------
initial
  begin
     CLK_50MHz = 1'b0;
     forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz
  end
 
initial
  begin
     RESET         = 1'b0;
     #100 RESET    = 1'b1;
     #600 RESET    = 1'b0;
  end
 
//
// Global initialization
//------------------------------
initial
  begin
     error         = 0;
     stimulus_done = 1;
     SW7           = 1'b0;  // Slide Switches
     SW6           = 1'b0;
     SW5           = 1'b0;
     SW4           = 1'b0;
     SW3           = 1'b0;
     SW2           = 1'b0;
     SW1           = 1'b0;
     SW0           = 1'b0;
     BTN2          = 1'b0;  // Push Button Switches
     BTN1          = 1'b0;
     BTN0          = 1'b0;
     UART_RXD      = 1'b0;  // UART
  end
 
//
// openMSP430 FPGA Instance
//----------------------------------
 
openMSP430_fpga dut (
 
// Clock Sources
    .CLK_50MHz    (CLK_50MHz),
    .CLK_SOCKET   (1'b0),
 
// Slide Switches
    .SW7          (SW7),
    .SW6          (SW6),
    .SW5          (SW5),
    .SW4          (SW4),
    .SW3          (SW3),
    .SW2          (SW2),
    .SW1          (SW1),
    .SW0          (SW0),
 
// Push Button Switches
    .BTN3         (RESET),
    .BTN2         (BTN2),
    .BTN1         (BTN1),
    .BTN0         (BTN0),
 
// LEDs
    .LED7         (LED7),
    .LED6         (LED6),
    .LED5         (LED5),
    .LED4         (LED4),
    .LED3         (LED3),
    .LED2         (LED2),
    .LED1         (LED1),
    .LED0         (LED0),
 
// Four-Sigit, Seven-Segment LED Display
    .SEG_A        (SEG_A),
    .SEG_B        (SEG_B),
    .SEG_C        (SEG_C),
    .SEG_D        (SEG_D),
    .SEG_E        (SEG_E),
    .SEG_F        (SEG_F),
    .SEG_G        (SEG_G),
    .SEG_DP       (SEG_DP),
    .SEG_AN0      (SEG_AN0),
    .SEG_AN1      (SEG_AN1),
    .SEG_AN2      (SEG_AN2),
    .SEG_AN3      (SEG_AN3),
 
// RS-232 Port
    .UART_RXD     (UART_RXD),
    .UART_TXD     (UART_TXD),
    .UART_RXD_A   (1'b0),
    .UART_TXD_A   (UART_TXD_A),
 
// PS/2 Mouse/Keyboard Port
    .PS2_D        (PS2_D),
    .PS2_C        (PS2_C),
 
// Fast, Asynchronous SRAM
    .SRAM_A17     (SRAM_A17),     // Address Bus Connections
    .SRAM_A16     (SRAM_A16),
    .SRAM_A15     (SRAM_A15),
    .SRAM_A14     (SRAM_A14),
    .SRAM_A13     (SRAM_A13),
    .SRAM_A12     (SRAM_A12),
    .SRAM_A11     (SRAM_A11),
    .SRAM_A10     (SRAM_A10),
    .SRAM_A9      (SRAM_A9),
    .SRAM_A8      (SRAM_A8),
    .SRAM_A7      (SRAM_A7),
    .SRAM_A6      (SRAM_A6),
    .SRAM_A5      (SRAM_A5),
    .SRAM_A4      (SRAM_A4),
    .SRAM_A3      (SRAM_A3),
    .SRAM_A2      (SRAM_A2),
    .SRAM_A1      (SRAM_A1),
    .SRAM_A0      (SRAM_A0),
    .SRAM_OE      (SRAM_OE),       // Write enable and output enable control signals
    .SRAM_WE      (SRAM_WE),
    .SRAM0_IO15   (SRAM0_IO15),    // SRAM Data signals, chip enables, and byte enables
    .SRAM0_IO14   (SRAM0_IO14),
    .SRAM0_IO13   (SRAM0_IO13),
    .SRAM0_IO12   (SRAM0_IO12),
    .SRAM0_IO11   (SRAM0_IO11),
    .SRAM0_IO10   (SRAM0_IO10),
    .SRAM0_IO9    (SRAM0_IO9),
    .SRAM0_IO8    (SRAM0_IO8),
    .SRAM0_IO7    (SRAM0_IO7),
    .SRAM0_IO6    (SRAM0_IO6),
    .SRAM0_IO5    (SRAM0_IO5),
    .SRAM0_IO4    (SRAM0_IO4),
    .SRAM0_IO3    (SRAM0_IO3),
    .SRAM0_IO2    (SRAM0_IO2),
    .SRAM0_IO1    (SRAM0_IO1),
    .SRAM0_IO0    (SRAM0_IO0),
    .SRAM0_CE1    (SRAM0_CE1),
    .SRAM0_UB1    (SRAM0_UB1),
    .SRAM0_LB1    (SRAM0_LB1),
    .SRAM1_IO15   (SRAM1_IO15),
    .SRAM1_IO14   (SRAM1_IO14),
    .SRAM1_IO13   (SRAM1_IO13),
    .SRAM1_IO12   (SRAM1_IO12),
    .SRAM1_IO11   (SRAM1_IO11),
    .SRAM1_IO10   (SRAM1_IO10),
    .SRAM1_IO9    (SRAM1_IO9),
    .SRAM1_IO8    (SRAM1_IO8),
    .SRAM1_IO7    (SRAM1_IO7),
    .SRAM1_IO6    (SRAM1_IO6),
    .SRAM1_IO5    (SRAM1_IO5),
    .SRAM1_IO4    (SRAM1_IO4),
    .SRAM1_IO3    (SRAM1_IO3),
    .SRAM1_IO2    (SRAM1_IO2),
    .SRAM1_IO1    (SRAM1_IO1),
    .SRAM1_IO0    (SRAM1_IO0),
    .SRAM1_CE2    (SRAM1_CE2),
    .SRAM1_UB2    (SRAM1_UB2),
    .SRAM1_LB2    (SRAM1_LB2),
 
// VGA Port
    .VGA_R        (VGA_R),
    .VGA_G        (VGA_G),
    .VGA_B        (VGA_B),
    .VGA_HS       (VGA_HS),
    .VGA_VS       (VGA_VS)
);
 
 
//
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_0 (
 
// OUTPUTs
    .e_state      (e_state),       // Execution state
    .i_state      (i_state),       // Instruction fetch state
    .inst_cycle   (inst_cycle),    // Cycle number within current instruction
    .inst_full    (inst_full),     // Currently executed instruction (full version)
    .inst_number  (inst_number),   // Instruction number since last system reset
    .inst_pc      (inst_pc),       // Instruction Program counter
    .inst_short   (inst_short),    // Currently executed instruction (short version)
 
// INPUTs
    .mclk         (mclk),          // Main system clock
    .puc_rst      (puc_rst)        // Main system reset
);
 
//
// Generate Waveform
//----------------------------------------
initial
  begin
   `ifdef VPD_FILE
     $vcdplusfile("tb_openMSP430_fpga.vpd");
     $vcdpluson();
   `else
     `ifdef TRN_FILE
        $recordfile ("tb_openMSP430_fpga.trn");
        $recordvars;
     `else
        $dumpfile("tb_openMSP430_fpga.vcd");
        $dumpvars(0, tb_openMSP430_fpga);
     `endif
   `endif
  end
 
//
// End of simulation
//----------------------------------------
 
initial // Timeout
  begin
     #500000;
     $display(" ===============================================");
     $display("|               SIMULATION FAILED               |");
     $display("|              (simulation Timeout)             |");
     $display(" ===============================================");
     $finish;
  end
 
initial // Normal end of test
  begin
     @(inst_pc===16'hffff)
     $display(" ===============================================");
     if (error!=0)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (some verilog stimulus checks failed)     |");
       end
     else if (~stimulus_done)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (the verilog stimulus didn't complete)    |");
       end
     else
       begin
          $display("|               SIMULATION PASSED               |");
       end
     $display(" ===============================================");
     $finish;
  end
 
 
//
// Tasks Definition
//------------------------------
 
   task tb_error;
      input [65*8:0] error_string;
      begin
         $display("ERROR: %s %t", error_string, $time);
         error = error+1;
      end
   endtask
 
 
endmodule

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 111

Line No.	Rev	Author	Line
1	2	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: tb_openMSP430_fpga.v`
26			`//`
27			`// *Module Description:`
28			`// openMSP430 FPGA testbench`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34	16	olivier.gi	`// $Rev: 111 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $`
37			`//----------------------------------------------------------------------------`
38	23	olivier.gi	`include "timescale.v"
39	104	olivier.gi	`ifdef OMSP_NO_INCLUDE
40			`else
41	23	olivier.gi	`include "openMSP430_defines.v"
42	104	olivier.gi	`endif
43	2	olivier.gi
44			`module tb_openMSP430_fpga;`
45
46			`//`
47			`// Wire & Register definition`
48			`//------------------------------`
49
50			`// Clock & Reset`
51			`reg CLK_50MHz;`
52			`reg RESET;`
53
54			`// Slide Switches`
55			`reg SW7;`
56			`reg SW6;`
57			`reg SW5;`
58			`reg SW4;`
59			`reg SW3;`
60			`reg SW2;`
61			`reg SW1;`
62			`reg SW0;`
63
64			`// Push Button Switches`
65			`reg BTN2;`
66			`reg BTN1;`
67			`reg BTN0;`
68
69			`// LEDs`
70			`wire LED7;`
71			`wire LED6;`
72			`wire LED5;`
73			`wire LED4;`
74			`wire LED3;`
75			`wire LED2;`
76			`wire LED1;`
77			`wire LED0;`
78
79			`// Four-Sigit, Seven-Segment LED Display`
80			`wire SEG_A;`
81			`wire SEG_B;`
82			`wire SEG_C;`
83			`wire SEG_D;`
84			`wire SEG_E;`
85			`wire SEG_F;`
86			`wire SEG_G;`
87			`wire SEG_DP;`
88			`wire SEG_AN0;`
89			`wire SEG_AN1;`
90			`wire SEG_AN2;`
91			`wire SEG_AN3;`
92
93			`// UART`
94			`reg UART_RXD;`
95			`wire UART_TXD;`
96
97			`// Core debug signals`
98			`wire [8*32-1:0] i_state;`
99			`wire [8*32-1:0] e_state;`
100			`wire [31:0] inst_cycle;`
101			`wire [8*32-1:0] inst_full;`
102			`wire [31:0] inst_number;`
103			`wire [15:0] inst_pc;`
104			`wire [8*32-1:0] inst_short;`
105
106			`// Testbench variables`
107			`integer i;`
108			`integer error;`
109			`reg stimulus_done;`
110
111
112			`//`
113			`// Include files`
114			`//------------------------------`
115
116			`// CPU & Memory registers`
117			`include "registers.v"
118
119			`// Verilog stimulus`
120			`include "stimulus.v"
121
122			`//`
123	37	olivier.gi	`// Initialize Program Memory`
124	2	olivier.gi	`//------------------------------`
125
126			`initial`
127			`begin`
128			`// Read memory file`
129	94	olivier.gi	`#10 $readmemh("./pmem.mem", pmem);`
130	2	olivier.gi
131			`// Update Xilinx memory banks`
132			`for (i=0; i<2048; i=i+1)`
133			`begin`
134	37	olivier.gi	`dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];`
135			`dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];`
136	2	olivier.gi	`end`
137			`end`
138
139			`//`
140			`// Generate Clock & Reset`
141			`//------------------------------`
142			`initial`
143			`begin`
144			`CLK_50MHz = 1'b0;`
145			`forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz`
146			`end`
147
148			`initial`
149			`begin`
150			`RESET = 1'b0;`
151			`#100 RESET = 1'b1;`
152			`#600 RESET = 1'b0;`
153			`end`
154
155			`//`
156			`// Global initialization`
157			`//------------------------------`
158			`initial`
159			`begin`
160			`error = 0;`
161			`stimulus_done = 1;`
162			`SW7 = 1'b0; // Slide Switches`
163			`SW6 = 1'b0;`
164			`SW5 = 1'b0;`
165			`SW4 = 1'b0;`
166			`SW3 = 1'b0;`
167			`SW2 = 1'b0;`
168			`SW1 = 1'b0;`
169			`SW0 = 1'b0;`
170			`BTN2 = 1'b0; // Push Button Switches`
171			`BTN1 = 1'b0;`
172			`BTN0 = 1'b0;`
173			`UART_RXD = 1'b0; // UART`
174			`end`
175
176			`//`
177			`// openMSP430 FPGA Instance`
178			`//----------------------------------`
179
180			`openMSP430_fpga dut (`
181
182			`// Clock Sources`
183			`.CLK_50MHz (CLK_50MHz),`
184			`.CLK_SOCKET (1'b0),`
185
186			`// Slide Switches`
187			`.SW7 (SW7),`
188			`.SW6 (SW6),`
189			`.SW5 (SW5),`
190			`.SW4 (SW4),`
191			`.SW3 (SW3),`
192			`.SW2 (SW2),`
193			`.SW1 (SW1),`
194			`.SW0 (SW0),`
195
196			`// Push Button Switches`
197			`.BTN3 (RESET),`
198			`.BTN2 (BTN2),`
199			`.BTN1 (BTN1),`
200			`.BTN0 (BTN0),`
201
202			`// LEDs`
203			`.LED7 (LED7),`
204			`.LED6 (LED6),`
205			`.LED5 (LED5),`
206			`.LED4 (LED4),`
207			`.LED3 (LED3),`
208			`.LED2 (LED2),`
209			`.LED1 (LED1),`
210			`.LED0 (LED0),`
211
212			`// Four-Sigit, Seven-Segment LED Display`
213			`.SEG_A (SEG_A),`
214			`.SEG_B (SEG_B),`
215			`.SEG_C (SEG_C),`
216			`.SEG_D (SEG_D),`
217			`.SEG_E (SEG_E),`
218			`.SEG_F (SEG_F),`
219			`.SEG_G (SEG_G),`
220			`.SEG_DP (SEG_DP),`
221			`.SEG_AN0 (SEG_AN0),`
222			`.SEG_AN1 (SEG_AN1),`
223			`.SEG_AN2 (SEG_AN2),`
224			`.SEG_AN3 (SEG_AN3),`
225
226			`// RS-232 Port`
227			`.UART_RXD (UART_RXD),`
228			`.UART_TXD (UART_TXD),`
229			`.UART_RXD_A (1'b0),`
230			`.UART_TXD_A (UART_TXD_A),`
231
232			`// PS/2 Mouse/Keyboard Port`
233			`.PS2_D (PS2_D),`
234			`.PS2_C (PS2_C),`
235
236			`// Fast, Asynchronous SRAM`
237			`.SRAM_A17 (SRAM_A17), // Address Bus Connections`
238			`.SRAM_A16 (SRAM_A16),`
239			`.SRAM_A15 (SRAM_A15),`
240			`.SRAM_A14 (SRAM_A14),`
241			`.SRAM_A13 (SRAM_A13),`
242			`.SRAM_A12 (SRAM_A12),`
243			`.SRAM_A11 (SRAM_A11),`
244			`.SRAM_A10 (SRAM_A10),`
245			`.SRAM_A9 (SRAM_A9),`
246			`.SRAM_A8 (SRAM_A8),`
247			`.SRAM_A7 (SRAM_A7),`
248			`.SRAM_A6 (SRAM_A6),`
249			`.SRAM_A5 (SRAM_A5),`
250			`.SRAM_A4 (SRAM_A4),`
251			`.SRAM_A3 (SRAM_A3),`
252			`.SRAM_A2 (SRAM_A2),`
253			`.SRAM_A1 (SRAM_A1),`
254			`.SRAM_A0 (SRAM_A0),`
255			`.SRAM_OE (SRAM_OE), // Write enable and output enable control signals`
256			`.SRAM_WE (SRAM_WE),`
257			`.SRAM0_IO15 (SRAM0_IO15), // SRAM Data signals, chip enables, and byte enables`
258			`.SRAM0_IO14 (SRAM0_IO14),`
259			`.SRAM0_IO13 (SRAM0_IO13),`
260			`.SRAM0_IO12 (SRAM0_IO12),`
261			`.SRAM0_IO11 (SRAM0_IO11),`
262			`.SRAM0_IO10 (SRAM0_IO10),`
263			`.SRAM0_IO9 (SRAM0_IO9),`
264			`.SRAM0_IO8 (SRAM0_IO8),`
265			`.SRAM0_IO7 (SRAM0_IO7),`
266			`.SRAM0_IO6 (SRAM0_IO6),`
267			`.SRAM0_IO5 (SRAM0_IO5),`
268			`.SRAM0_IO4 (SRAM0_IO4),`
269			`.SRAM0_IO3 (SRAM0_IO3),`
270			`.SRAM0_IO2 (SRAM0_IO2),`
271			`.SRAM0_IO1 (SRAM0_IO1),`
272			`.SRAM0_IO0 (SRAM0_IO0),`
273			`.SRAM0_CE1 (SRAM0_CE1),`
274			`.SRAM0_UB1 (SRAM0_UB1),`
275			`.SRAM0_LB1 (SRAM0_LB1),`
276			`.SRAM1_IO15 (SRAM1_IO15),`
277			`.SRAM1_IO14 (SRAM1_IO14),`
278			`.SRAM1_IO13 (SRAM1_IO13),`
279			`.SRAM1_IO12 (SRAM1_IO12),`
280			`.SRAM1_IO11 (SRAM1_IO11),`
281			`.SRAM1_IO10 (SRAM1_IO10),`
282			`.SRAM1_IO9 (SRAM1_IO9),`
283			`.SRAM1_IO8 (SRAM1_IO8),`
284			`.SRAM1_IO7 (SRAM1_IO7),`
285			`.SRAM1_IO6 (SRAM1_IO6),`
286			`.SRAM1_IO5 (SRAM1_IO5),`
287			`.SRAM1_IO4 (SRAM1_IO4),`
288			`.SRAM1_IO3 (SRAM1_IO3),`
289			`.SRAM1_IO2 (SRAM1_IO2),`
290			`.SRAM1_IO1 (SRAM1_IO1),`
291			`.SRAM1_IO0 (SRAM1_IO0),`
292			`.SRAM1_CE2 (SRAM1_CE2),`
293			`.SRAM1_UB2 (SRAM1_UB2),`
294			`.SRAM1_LB2 (SRAM1_LB2),`
295
296			`// VGA Port`
297			`.VGA_R (VGA_R),`
298			`.VGA_G (VGA_G),`
299			`.VGA_B (VGA_B),`
300			`.VGA_HS (VGA_HS),`
301			`.VGA_VS (VGA_VS)`
302			`);`
303
304
305			`//`
306			`// Debug utility signals`
307			`//----------------------------------------`
308			`msp_debug msp_debug_0 (`
309
310			`// OUTPUTs`
311			`.e_state (e_state), // Execution state`
312			`.i_state (i_state), // Instruction fetch state`
313			`.inst_cycle (inst_cycle), // Cycle number within current instruction`
314			`.inst_full (inst_full), // Currently executed instruction (full version)`
315			`.inst_number (inst_number), // Instruction number since last system reset`
316			`.inst_pc (inst_pc), // Instruction Program counter`
317			`.inst_short (inst_short), // Currently executed instruction (short version)`
318
319			`// INPUTs`
320			`.mclk (mclk), // Main system clock`
321	111	olivier.gi	`.puc_rst (puc_rst) // Main system reset`
322	2	olivier.gi	`);`
323
324			`//`
325			`// Generate Waveform`
326			`//----------------------------------------`
327			`initial`
328			`begin`
329			`ifdef VPD_FILE
330			`$vcdplusfile("tb_openMSP430_fpga.vpd");`
331			`$vcdpluson();`
332			`else
333	98	olivier.gi	`ifdef TRN_FILE
334			`$recordfile ("tb_openMSP430_fpga.trn");`
335			`$recordvars;`
336			`else
337			`$dumpfile("tb_openMSP430_fpga.vcd");`
338			`$dumpvars(0, tb_openMSP430_fpga);`
339			`endif
340	2	olivier.gi	`endif
341			`end`
342
343			`//`
344			`// End of simulation`
345			`//----------------------------------------`
346
347			`initial // Timeout`
348			`begin`
349			`#500000;`
350			`$display(" ===============================================");`
351			`$display("\| SIMULATION FAILED \|");`
352			`$display("\| (simulation Timeout) \|");`
353			`$display(" ===============================================");`
354			`$finish;`
355			`end`
356
357			`initial // Normal end of test`
358			`begin`
359			`@(inst_pc===16'hffff)`
360			`$display(" ===============================================");`
361			`if (error!=0)`
362			`begin`
363			`$display("\| SIMULATION FAILED \|");`
364			`$display("\| (some verilog stimulus checks failed) \|");`
365			`end`
366			`else if (~stimulus_done)`
367			`begin`
368			`$display("\| SIMULATION FAILED \|");`
369			`$display("\| (the verilog stimulus didn't complete) \|");`
370			`end`
371			`else`
372			`begin`
373			`$display("\| SIMULATION PASSED \|");`
374			`end`
375			`$display(" ===============================================");`
376			`$finish;`
377			`end`
378
379
380			`//`
381			`// Tasks Definition`
382			`//------------------------------`
383
384			`task tb_error;`
385			`input [65*8:0] error_string;`
386			`begin`
387			`$display("ERROR: %s %t", error_string, $time);`
388			`error = error+1;`
389			`end`
390			`endtask`
391
392
393			`endmodule`