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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [coregen.cgp] - Blame information for rev 28

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Line No. Rev Author Line
1 2 olivier.gi 
# Date: Mon Apr  6 14:50:01 2009
2 
SET addpads = False
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = Verilog
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SET device = xc3s200
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SET devicefamily = spartan3
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SET flowvendor = Foundation_iSE
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ft256
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -4
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SET verilogsim = True
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SET vhdlsim = False
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SET workingdirectory = /home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/tmp
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