URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [coregen.cgp] - Blame information for rev 112

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# Date: Mon Apr  6 14:50:01 2009
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = Verilog
SET device = xc3s200
SET devicefamily = spartan3
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ft256
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = False
SET workingdirectory = /home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/tmp
 

Line No.	Rev	Author	Line
1	2	olivier.gi	`# Date: Mon Apr 6 14:50:01 2009`
2			`SET addpads = False`
3			`SET asysymbol = True`
4			`SET busformat = BusFormatAngleBracketNotRipped`
5			`SET createndf = False`
6			`SET designentry = Verilog`
7			`SET device = xc3s200`
8			`SET devicefamily = spartan3`
9			`SET flowvendor = Foundation_iSE`
10			`SET formalverification = False`
11			`SET foundationsym = False`
12			`SET implementationfiletype = Ngc`
13			`SET package = ft256`
14			`SET removerpms = False`
15			`SET simulationfiles = Behavioral`
16			`SET speedgrade = -4`
17			`SET verilogsim = True`
18			`SET vhdlsim = False`
19			`SET workingdirectory = /home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/tmp`
20

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [coregen.cgp] - Blame information for rev 112