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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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olivier.gi |
Welcome to Xilinx CORE Generator.
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Opened project file
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/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coreg
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en/coregen.cgp.
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Customizing IP...
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WARNING! Program tries to unlock a connection without having acquired
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| 7 |
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a lock first, which indicates a programming error.
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There will be no further warnings about this issue.
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libxcb: WARNING! Program tries to lock an already locked connection,
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which indicates a programming error.
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There will be no further warnings about this issue.
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| 12 |
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Finished Customizing.
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Generating IP...
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WARNING! Program tries to unlock a connection without having acquired
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| 15 |
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a lock first, which indicates a programming error.
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| 16 |
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There will be no further warnings about this issue.
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| 17 |
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libxcb: WARNING! Program tries to lock an already locked connection,
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| 18 |
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which indicates a programming error.
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| 19 |
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There will be no further warnings about this issue.
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| 20 |
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Generating Implementation files.
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Generating ISE symbol file...
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Generating NGC file.
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Finished Generating.
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Successfully generated rom_8x2k_hi.
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Customizing IP...
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| 26 |
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Finished Customizing.
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| 27 |
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Generating IP...
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| 28 |
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WARNING! Program tries to unlock a connection without having acquired
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| 29 |
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a lock first, which indicates a programming error.
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| 30 |
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There will be no further warnings about this issue.
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| 31 |
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libxcb: WARNING! Program tries to lock an already locked connection,
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| 32 |
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which indicates a programming error.
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| 33 |
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There will be no further warnings about this issue.
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| 34 |
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Generating Implementation files.
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| 35 |
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Generating ISE symbol file...
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| 36 |
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Generating NGC file.
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| 37 |
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Finished Generating.
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| 38 |
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Successfully generated rom_8x2k_lo.
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| 39 |
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Closed project file.
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