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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [coregen.log] - Blame information for rev 227

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Line No. Rev Author Line
1 2 olivier.gi
Welcome to Xilinx CORE Generator.
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Opened project file
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/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coreg
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en/coregen.cgp.
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Customizing IP...
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 WARNING! Program tries to unlock a connection without having acquired
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        a lock first, which indicates a programming error.
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        There will be no further warnings about this issue.
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libxcb: WARNING! Program tries to lock an already locked connection,
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        which indicates a programming error.
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        There will be no further warnings about this issue.
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Finished Customizing.
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Generating IP...
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 WARNING! Program tries to unlock a connection without having acquired
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        a lock first, which indicates a programming error.
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        There will be no further warnings about this issue.
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libxcb: WARNING! Program tries to lock an already locked connection,
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        which indicates a programming error.
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        There will be no further warnings about this issue.
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Generating Implementation files.
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Generating ISE symbol file...
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Generating NGC file.
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Finished Generating.
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Successfully generated rom_8x2k_hi.
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Customizing IP...
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Finished Customizing.
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Generating IP...
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 WARNING! Program tries to unlock a connection without having acquired
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        a lock first, which indicates a programming error.
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        There will be no further warnings about this issue.
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libxcb: WARNING! Program tries to lock an already locked connection,
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        which indicates a programming error.
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        There will be no further warnings about this issue.
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Generating Implementation files.
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Generating ISE symbol file...
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Generating NGC file.
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Finished Generating.
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Successfully generated rom_8x2k_lo.
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Closed project file.

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