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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [ram_8x512_hi.sym] - Blame information for rev 28

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Line No. Rev Author Line
1 2 olivier.gi 
VERSION 5
2 
BEGIN SYMBOL ram_8x512_hi
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SYMBOLTYPE BLOCK
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TIMESTAMP 2009 4 6 14 52 20
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SYMPIN 0 48 Input addr[8:0]
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SYMPIN 0 80 Input din[7:0]
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SYMPIN 0 112 Input we
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SYMPIN 0 144 Input en
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SYMPIN 0 240 Input clk
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SYMPIN 352 48 Output dout[7:0]
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RECTANGLE N 32 0 320 272
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BEGIN DISPLAY 36 48 PIN addr[8:0] ATTR PinName
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    FONT 24 "Arial"
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END DISPLAY
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BEGIN LINE W 0 48 32 48
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END LINE
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BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName
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    FONT 24 "Arial"
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END DISPLAY
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BEGIN LINE W 0 80 32 80
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END LINE
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BEGIN DISPLAY 36 112 PIN we ATTR PinName
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    FONT 24 "Arial"
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END DISPLAY
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LINE N 0 112 32 112
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BEGIN DISPLAY 36 144 PIN en ATTR PinName
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    FONT 24 "Arial"
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END DISPLAY
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LINE N 0 144 32 144
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BEGIN DISPLAY 36 240 PIN clk ATTR PinName
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    FONT 24 "Arial"
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END DISPLAY
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LINE N 0 240 32 240
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BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName
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    ALIGNMENT RIGHT
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    FONT 24 "Arial"
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END DISPLAY
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BEGIN LINE W 320 48 352 48
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END LINE
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END SYMBOL

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