Subversion Repositories openmsp430

/*******************************************************************************

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// The following must be inserted into your Verilog file for this

// core to be instantiated. Change the instance name and port connections

// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

ram_8x512_hi YourInstanceName (

        .addr(addr), // Bus [8 : 0]

        .clk(clk),

        .din(din), // Bus [7 : 0]

        .dout(dout), // Bus [7 : 0]

        .en(en),

        .we(we));

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file ram_8x512_hi.v when simulating

// the core, ram_8x512_hi. When compiling the wrapper file, be sure to

// reference the XilinxCoreLib Verilog simulation library. For detailed

// instructions, please refer to the "CORE Generator Help".