OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [rom_8x2k_lo.asy] - Blame information for rev 28

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
Version 4
2
SymbolType BLOCK
3
RECTANGLE Normal 32 0 320 272
4
PIN 0 48  LEFT 36
5
PINATTR PinName addr[10:0]
6
PINATTR Polarity IN
7
LINE Wide 0 48 32 48
8
PIN 0 80  LEFT 36
9
PINATTR PinName din[7:0]
10
PINATTR Polarity IN
11
LINE Wide 0 80 32 80
12
PIN 0 112  LEFT 36
13
PINATTR PinName we
14
PINATTR Polarity IN
15
LINE Normal 0 112 32 112
16
PIN 0 144  LEFT 36
17
PINATTR PinName en
18
PINATTR Polarity IN
19
LINE Normal 0 144 32 144
20
PIN 0 240  LEFT 36
21
PINATTR PinName clk
22
PINATTR Polarity IN
23
LINE Normal 0 240 32 240
24
PIN 352 48  RIGHT 36
25
PINATTR PinName dout[7:0]
26
PINATTR Polarity OUT
27
LINE Wide 320 48 352 48

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.