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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [driver_7segment.v] - Blame information for rev 2

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1 2 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: driver_7segment.v
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// 
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// *Module Description:
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//                      Driver for the four-digit, seven-segment LED display.
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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`timescale 1ns / 100ps
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module  driver_7segment (
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// OUTPUTs
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    per_dout,                       // Peripheral data output
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    seg_a,                          // Segment A control
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    seg_b,                          // Segment B control
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    seg_c,                          // Segment C control
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    seg_d,                          // Segment D control
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    seg_e,                          // Segment E control
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    seg_f,                          // Segment F control
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    seg_g,                          // Segment G control
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    seg_dp,                         // Segment DP control
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    seg_an0,                        // Anode 0 control
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    seg_an1,                        // Anode 1 control
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    seg_an2,                        // Anode 2 control
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    seg_an3,                        // Anode 3 control
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// INPUTs
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    mclk,                           // Main system clock
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    per_addr,                       // Peripheral address
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    per_din,                        // Peripheral data input
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    per_en,                         // Peripheral enable (high active)
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    per_wen,                        // Peripheral write enable (high active)
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    puc                             // Main system reset
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);
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// OUTPUTs
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//=========
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output      [15:0] per_dout;        // Peripheral data output
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output             seg_a;           // Segment A control
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output             seg_b;           // Segment B control
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output             seg_c;           // Segment C control
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output             seg_d;           // Segment D control
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output             seg_e;           // Segment E control
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output             seg_f;           // Segment F control
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output             seg_g;           // Segment G control
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output             seg_dp;          // Segment DP control
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output             seg_an0;         // Anode 0 control
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output             seg_an1;         // Anode 1 control
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output             seg_an2;         // Anode 2 control
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output             seg_an3;         // Anode 3 control
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// INPUTs
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//=========
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input              mclk;            // Main system clock
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input        [7:0] per_addr;        // Peripheral address
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input       [15:0] per_din;         // Peripheral data input
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input              per_en;          // Peripheral enable (high active)
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input        [1:0] per_wen;         // Peripheral write enable (high active)
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input              puc;             // Main system reset
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//=============================================================================
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// 1)  PARAMETER DECLARATION
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//=============================================================================
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// Register addresses
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parameter          DIGIT0    = 9'h090;
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parameter          DIGIT1    = 9'h091;
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parameter          DIGIT2    = 9'h092;
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parameter          DIGIT3    = 9'h093;
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// Register one-hot decoder
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parameter          DIGIT0_D  = (256'h1 << (DIGIT0 /2));
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parameter          DIGIT1_D  = (256'h1 << (DIGIT1 /2));
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parameter          DIGIT2_D  = (256'h1 << (DIGIT2 /2));
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parameter          DIGIT3_D  = (256'h1 << (DIGIT3 /2));
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//============================================================================
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// 2)  REGISTER DECODER
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//============================================================================
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// Register address decode
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reg  [255:0]  reg_dec;
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always @(per_addr)
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  case (per_addr)
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    (DIGIT0 /2):   reg_dec   = DIGIT0_D;
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    (DIGIT1 /2):   reg_dec   = DIGIT1_D;
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    (DIGIT2 /2):   reg_dec   = DIGIT2_D;
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    (DIGIT3 /2):   reg_dec   = DIGIT3_D;
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    default    :   reg_dec   = {256{1'b0}};
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  endcase
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// Read/Write probes
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wire         reg_lo_write =  per_wen[0] & per_en;
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wire         reg_hi_write =  per_wen[1] & per_en;
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wire         reg_read     = ~|per_wen   & per_en;
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// Read/Write vectors
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wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
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wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
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wire [255:0] reg_rd       = reg_dec & {256{reg_read}};
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//============================================================================
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// 3) REGISTERS
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//============================================================================
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// DIGIT0 Register
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//-----------------
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reg  [7:0] digit0;
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wire       digit0_wr  = DIGIT0[0] ? reg_hi_wr[DIGIT0/2] : reg_lo_wr[DIGIT0/2];
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wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8]       : per_din[7:0];
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always @ (posedge mclk or posedge puc)
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  if (puc)            digit0 <=  8'h00;
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  else if (digit0_wr) digit0 <=  digit0_nxt;
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// DIGIT1 Register
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//-----------------
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reg  [7:0] digit1;
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wire       digit1_wr  = DIGIT1[0] ? reg_hi_wr[DIGIT1/2] : reg_lo_wr[DIGIT1/2];
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wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8]       : per_din[7:0];
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always @ (posedge mclk or posedge puc)
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  if (puc)            digit1 <=  8'h00;
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  else if (digit1_wr) digit1 <=  digit1_nxt;
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// DIGIT2 Register
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//-----------------
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reg  [7:0] digit2;
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wire       digit2_wr  = DIGIT2[0] ? reg_hi_wr[DIGIT2/2] : reg_lo_wr[DIGIT2/2];
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wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8]       : per_din[7:0];
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always @ (posedge mclk or posedge puc)
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  if (puc)            digit2 <=  8'h00;
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  else if (digit2_wr) digit2 <=  digit2_nxt;
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// DIGIT3 Register
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//-----------------
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reg  [7:0] digit3;
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wire       digit3_wr  = DIGIT3[0] ? reg_hi_wr[DIGIT3/2] : reg_lo_wr[DIGIT3/2];
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wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8]       : per_din[7:0];
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always @ (posedge mclk or posedge puc)
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  if (puc)            digit3 <=  8'h00;
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  else if (digit3_wr) digit3 <=  digit3_nxt;
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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// Data output mux
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wire [15:0] digit0_rd   = (digit0  & {8{reg_rd[DIGIT0/2]}})  << (8 & {4{DIGIT0[0]}});
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wire [15:0] digit1_rd   = (digit1  & {8{reg_rd[DIGIT1/2]}})  << (8 & {4{DIGIT1[0]}});
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wire [15:0] digit2_rd   = (digit2  & {8{reg_rd[DIGIT2/2]}})  << (8 & {4{DIGIT2[0]}});
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wire [15:0] digit3_rd   = (digit3  & {8{reg_rd[DIGIT3/2]}})  << (8 & {4{DIGIT3[0]}});
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wire [15:0] per_dout  =  digit0_rd  |
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                         digit1_rd  |
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                         digit2_rd  |
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                         digit3_rd;
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//============================================================================
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// 5) FOUR-DIGIT, SEVEN-SEGMENT LED DISPLAY DRIVER
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//============================================================================
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// Anode selection
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//------------------
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// Free running counter
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reg [23:0] anode_cnt;
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always @ (posedge mclk or posedge puc)
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if (puc) anode_cnt <=  24'h00_0000;
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else     anode_cnt <=  anode_cnt+24'h00_0001;
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// Anode selection
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wire [3:0] seg_an  = (4'h1 << anode_cnt[17:16]);
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wire       seg_an0 = ~seg_an[0];
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wire       seg_an1 = ~seg_an[1];
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wire       seg_an2 = ~seg_an[2];
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wire       seg_an3 = ~seg_an[3];
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// Segment selection
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//----------------------------
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wire [7:0] digit  = seg_an[0] ? digit0 :
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                    seg_an[1] ? digit1 :
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                    seg_an[2] ? digit2 :
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                                digit3;
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wire       seg_a  = ~digit[7];
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wire       seg_b  = ~digit[6];
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wire       seg_c  = ~digit[5];
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wire       seg_d  = ~digit[4];
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wire       seg_e  = ~digit[3];
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wire       seg_f  = ~digit[2];
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wire       seg_g  = ~digit[1];
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wire       seg_dp = ~digit[0];
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endmodule // driver_7segment
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