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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [io_mux.v] - Blame information for rev 2

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1 2 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: io_mux.v
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// 
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// *Module Description:
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//                      I/O mux for port function selection.
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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`timescale 1ns / 100ps
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module  io_mux (
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// Function A (typically GPIO)
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    a_din,
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    a_dout,
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    a_dout_en,
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// Function B (Timer A, ...)
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    b_din,
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    b_dout,
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    b_dout_en,
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// IO Cell
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    io_din,
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    io_dout,
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    io_dout_en,
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// Function selection (0=A, 1=B)
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    sel
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);
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// PARAMETERs
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//============
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parameter          WIDTH = 8;
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// Function A (typically GPIO)
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//===============================
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output [WIDTH-1:0] a_din;
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input  [WIDTH-1:0] a_dout;
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input  [WIDTH-1:0] a_dout_en;
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// Function B (Timer A, ...)
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//===============================
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output [WIDTH-1:0] b_din;
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input  [WIDTH-1:0] b_dout;
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input  [WIDTH-1:0] b_dout_en;
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// IO Cell
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//===============================
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input  [WIDTH-1:0] io_din;
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output [WIDTH-1:0] io_dout;
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output [WIDTH-1:0] io_dout_en;
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// Function selection (0=A, 1=B)
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//===============================
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input  [WIDTH-1:0] sel;
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//=============================================================================
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// 1)  I/O FUNCTION SELECTION MUX
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//=============================================================================
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function [WIDTH-1:0] mux (
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   input [WIDTH-1:0] A,
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   input [WIDTH-1:0] B,
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   input [WIDTH-1:0] SEL
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);
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   integer i;
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   begin
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      mux = {WIDTH{1'b0}};
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      for (i = 0; i < WIDTH; i = i + 1)
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        mux[i] = sel[i] ? B[i] : A[i];
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   end
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endfunction
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assign a_din      = mux(       io_din, {WIDTH{1'b0}}, sel);
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assign b_din      = mux({WIDTH{1'b0}},        io_din, sel);
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assign io_dout    = mux(       a_dout,        b_dout, sel);
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assign io_dout_en = mux(    a_dout_en,     b_dout_en, sel);
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endmodule // io_mux

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