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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openMSP430_fpga.v] - Blame information for rev 104

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1 2 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
// 
25
// *File Name: openMSP430_fpga.v
26
// 
27
// *Module Description:
28
//                      openMSP430 FPGA Top-level for the Diligent
29
//                     Spartan-3 starter kit.
30
//
31
// *Author(s):
32
//              - Olivier Girard,    olgirard@gmail.com
33
//
34
//----------------------------------------------------------------------------
35 16 olivier.gi
// $Rev: 104 $
36
// $LastChangedBy: olivier.girard $
37
// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
38
//----------------------------------------------------------------------------
39 23 olivier.gi
`include "openMSP430_defines.v"
40 2 olivier.gi
 
41
module openMSP430_fpga (
42
 
43
// Clock Sources
44
    CLK_50MHz,
45
    CLK_SOCKET,
46
 
47
// Slide Switches
48
    SW7,
49
    SW6,
50
    SW5,
51
    SW4,
52
    SW3,
53
    SW2,
54
    SW1,
55
    SW0,
56
 
57
// Push Button Switches
58
    BTN3,
59
    BTN2,
60
    BTN1,
61
    BTN0,
62
 
63
// LEDs
64
    LED7,
65
    LED6,
66
    LED5,
67
    LED4,
68
    LED3,
69
    LED2,
70
    LED1,
71
    LED0,
72
 
73
// Four-Sigit, Seven-Segment LED Display
74
    SEG_A,
75
    SEG_B,
76
    SEG_C,
77
    SEG_D,
78
    SEG_E,
79
    SEG_F,
80
    SEG_G,
81
    SEG_DP,
82
    SEG_AN0,
83
    SEG_AN1,
84
    SEG_AN2,
85
    SEG_AN3,
86
 
87
// RS-232 Port
88
    UART_RXD,
89
    UART_TXD,
90
    UART_RXD_A,
91
    UART_TXD_A,
92
 
93
// PS/2 Mouse/Keyboard Port
94
    PS2_D,
95
    PS2_C,
96
 
97
// Fast, Asynchronous SRAM
98
    SRAM_A17,               // Address Bus Connections
99
    SRAM_A16,
100
    SRAM_A15,
101
    SRAM_A14,
102
    SRAM_A13,
103
    SRAM_A12,
104
    SRAM_A11,
105
    SRAM_A10,
106
    SRAM_A9,
107
    SRAM_A8,
108
    SRAM_A7,
109
    SRAM_A6,
110
    SRAM_A5,
111
    SRAM_A4,
112
    SRAM_A3,
113
    SRAM_A2,
114
    SRAM_A1,
115
    SRAM_A0,
116
    SRAM_OE,                // Write enable and output enable control signals
117
    SRAM_WE,
118
    SRAM0_IO15,             // SRAM Data signals, chip enables, and byte enables
119
    SRAM0_IO14,
120
    SRAM0_IO13,
121
    SRAM0_IO12,
122
    SRAM0_IO11,
123
    SRAM0_IO10,
124
    SRAM0_IO9,
125
    SRAM0_IO8,
126
    SRAM0_IO7,
127
    SRAM0_IO6,
128
    SRAM0_IO5,
129
    SRAM0_IO4,
130
    SRAM0_IO3,
131
    SRAM0_IO2,
132
    SRAM0_IO1,
133
    SRAM0_IO0,
134
    SRAM0_CE1,
135
    SRAM0_UB1,
136
    SRAM0_LB1,
137
    SRAM1_IO15,
138
    SRAM1_IO14,
139
    SRAM1_IO13,
140
    SRAM1_IO12,
141
    SRAM1_IO11,
142
    SRAM1_IO10,
143
    SRAM1_IO9,
144
    SRAM1_IO8,
145
    SRAM1_IO7,
146
    SRAM1_IO6,
147
    SRAM1_IO5,
148
    SRAM1_IO4,
149
    SRAM1_IO3,
150
    SRAM1_IO2,
151
    SRAM1_IO1,
152
    SRAM1_IO0,
153
    SRAM1_CE2,
154
    SRAM1_UB2,
155
    SRAM1_LB2,
156
 
157
// VGA Port
158
    VGA_R,
159
    VGA_G,
160
    VGA_B,
161
    VGA_HS,
162
    VGA_VS
163
);
164
 
165
// Clock Sources
166
input     CLK_50MHz;
167
input     CLK_SOCKET;
168
 
169
// Slide Switches
170
input     SW7;
171
input     SW6;
172
input     SW5;
173
input     SW4;
174
input     SW3;
175
input     SW2;
176
input     SW1;
177
input     SW0;
178
 
179
// Push Button Switches
180
input     BTN3;
181
input     BTN2;
182
input     BTN1;
183
input     BTN0;
184
 
185
// LEDs
186
output    LED7;
187
output    LED6;
188
output    LED5;
189
output    LED4;
190
output    LED3;
191
output    LED2;
192
output    LED1;
193
output    LED0;
194
 
195
// Four-Sigit, Seven-Segment LED Display
196
output    SEG_A;
197
output    SEG_B;
198
output    SEG_C;
199
output    SEG_D;
200
output    SEG_E;
201
output    SEG_F;
202
output    SEG_G;
203
output    SEG_DP;
204
output    SEG_AN0;
205
output    SEG_AN1;
206
output    SEG_AN2;
207
output    SEG_AN3;
208
 
209
// RS-232 Port
210
input     UART_RXD;
211
output    UART_TXD;
212
input     UART_RXD_A;
213
output    UART_TXD_A;
214
 
215
// PS/2 Mouse/Keyboard Port
216
inout     PS2_D;
217
output    PS2_C;
218
 
219
// Fast, Asynchronous SRAM
220
output    SRAM_A17;         // Address Bus Connections
221
output    SRAM_A16;
222
output    SRAM_A15;
223
output    SRAM_A14;
224
output    SRAM_A13;
225
output    SRAM_A12;
226
output    SRAM_A11;
227
output    SRAM_A10;
228
output    SRAM_A9;
229
output    SRAM_A8;
230
output    SRAM_A7;
231
output    SRAM_A6;
232
output    SRAM_A5;
233
output    SRAM_A4;
234
output    SRAM_A3;
235
output    SRAM_A2;
236
output    SRAM_A1;
237
output    SRAM_A0;
238
output    SRAM_OE;          // Write enable and output enable control signals
239
output    SRAM_WE;
240
inout     SRAM0_IO15;       // SRAM Data signals, chip enables, and byte enables
241
inout     SRAM0_IO14;
242
inout     SRAM0_IO13;
243
inout     SRAM0_IO12;
244
inout     SRAM0_IO11;
245
inout     SRAM0_IO10;
246
inout     SRAM0_IO9;
247
inout     SRAM0_IO8;
248
inout     SRAM0_IO7;
249
inout     SRAM0_IO6;
250
inout     SRAM0_IO5;
251
inout     SRAM0_IO4;
252
inout     SRAM0_IO3;
253
inout     SRAM0_IO2;
254
inout     SRAM0_IO1;
255
inout     SRAM0_IO0;
256
output    SRAM0_CE1;
257
output    SRAM0_UB1;
258
output    SRAM0_LB1;
259
inout     SRAM1_IO15;
260
inout     SRAM1_IO14;
261
inout     SRAM1_IO13;
262
inout     SRAM1_IO12;
263
inout     SRAM1_IO11;
264
inout     SRAM1_IO10;
265
inout     SRAM1_IO9;
266
inout     SRAM1_IO8;
267
inout     SRAM1_IO7;
268
inout     SRAM1_IO6;
269
inout     SRAM1_IO5;
270
inout     SRAM1_IO4;
271
inout     SRAM1_IO3;
272
inout     SRAM1_IO2;
273
inout     SRAM1_IO1;
274
inout     SRAM1_IO0;
275
output    SRAM1_CE2;
276
output    SRAM1_UB2;
277
output    SRAM1_LB2;
278
 
279
// VGA Port
280
output    VGA_R;
281
output    VGA_G;
282
output    VGA_B;
283
output    VGA_HS;
284
output    VGA_VS;
285
 
286
 
287
//=============================================================================
288
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
289
//=============================================================================
290
 
291
// openMSP430 output buses
292 37 olivier.gi
wire         [7:0] per_addr;
293
wire        [15:0] per_din;
294
wire         [1:0] per_wen;
295
wire [`DMEM_MSB:0] dmem_addr;
296
wire        [15:0] dmem_din;
297
wire         [1:0] dmem_wen;
298
wire [`PMEM_MSB:0] pmem_addr;
299
wire        [15:0] pmem_din;
300
wire         [1:0] pmem_wen;
301
wire        [13:0] irq_acc;
302 2 olivier.gi
 
303
// openMSP430 input buses
304 37 olivier.gi
wire        [13:0] irq_bus;
305
wire        [15:0] per_dout;
306
wire        [15:0] dmem_dout;
307
wire        [15:0] pmem_dout;
308 2 olivier.gi
 
309
// GPIO
310 37 olivier.gi
wire         [7:0] p1_din;
311
wire         [7:0] p1_dout;
312
wire         [7:0] p1_dout_en;
313
wire         [7:0] p1_sel;
314
wire         [7:0] p2_din;
315
wire         [7:0] p2_dout;
316
wire         [7:0] p2_dout_en;
317
wire         [7:0] p2_sel;
318
wire         [7:0] p3_din;
319
wire         [7:0] p3_dout;
320
wire         [7:0] p3_dout_en;
321
wire         [7:0] p3_sel;
322
wire        [15:0] per_dout_dio;
323 2 olivier.gi
 
324
// Timer A
325 37 olivier.gi
wire        [15:0] per_dout_tA;
326 2 olivier.gi
 
327
// 7 segment driver
328 37 olivier.gi
wire        [15:0] per_dout_7seg;
329 2 olivier.gi
 
330
// Others
331 37 olivier.gi
wire               reset_pin;
332 2 olivier.gi
 
333
 
334
//=============================================================================
335
// 2)  CLOCK GENERATION
336
//=============================================================================
337
 
338
// Input buffers
339
//------------------------
340
IBUFG ibuf_clk_main   (.O(clk_50M_in),    .I(CLK_50MHz));
341
IBUFG ibuf_clk_socket (.O(clk_socket_in), .I(CLK_SOCKET));
342
 
343
 
344
// Digital Clock Manager
345
//------------------------
346
 
347
// Generate 20MHz clock from 50MHz on-board oscillator
348
//`define DCM_FX_MODE
349
`ifdef DCM_FX_MODE
350
DCM dcm_adv_clk_main (
351
 
352
// OUTPUTs
353
    .CLK0         (),
354
    .CLK90        (),
355
    .CLK180       (),
356
    .CLK270       (),
357
    .CLK2X        (),
358
    .CLK2X180     (),
359
    .CLKDV        (),
360
    .CLKFX        (dcm_clk),
361
    .CLKFX180     (),
362
    .PSDONE       (),
363
    .STATUS       (),
364
    .LOCKED       (dcm_locked),
365
 
366
// INPUTs
367
    .CLKIN        (clk_50M_in),
368
    .CLKFB        (1'b0),
369
    .PSINCDEC     (1'b0),
370
    .PSEN         (1'b0),
371
    .DSSEN        (1'b0),
372
    .RST          (reset_pin),
373
    .PSCLK        (1'b0)
374
);
375
 
376
// synopsys translate_off
377
defparam dcm_adv_clk_main.CLK_FEEDBACK          = "NONE";
378
defparam dcm_adv_clk_main.CLKDV_DIVIDE          = 2.5;
379
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2     = "FALSE";
380
defparam dcm_adv_clk_main.CLKIN_PERIOD          = 20.0;
381
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT    = "NONE";
382
defparam dcm_adv_clk_main.DESKEW_ADJUST         = "SYSTEM_SYNCHRONOUS";
383
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE    = "LOW";
384
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE    = "LOW";
385
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
386
defparam dcm_adv_clk_main.FACTORY_JF            = 16'hC080;
387
defparam dcm_adv_clk_main.PHASE_SHIFT           = 0;
388
defparam dcm_adv_clk_main.STARTUP_WAIT          = "FALSE";
389
 
390
defparam dcm_adv_clk_main.CLKFX_DIVIDE          = 5;
391
defparam dcm_adv_clk_main.CLKFX_MULTIPLY        = 2;
392
// synopsys translate_on
393
`else
394
DCM dcm_adv_clk_main (
395
 
396
// OUTPUTs
397
    .CLKDV        (dcm_clk),
398
    .CLKFX        (),
399
    .CLKFX180     (),
400
    .CLK0         (CLK0_BUF),
401
    .CLK2X        (),
402
    .CLK2X180     (),
403
    .CLK90        (),
404
    .CLK180       (),
405
    .CLK270       (),
406
    .LOCKED       (dcm_locked),
407
    .PSDONE       (),
408
    .STATUS       (),
409
 
410
// INPUTs
411
    .CLKFB        (CLKFB_IN),
412
    .CLKIN        (clk_50M_in),
413
    .PSEN         (1'b0),
414
    .PSINCDEC     (1'b0),
415
    .DSSEN        (1'b0),
416
    .PSCLK        (1'b0),
417
    .RST          (reset_pin)
418
);
419
BUFG CLK0_BUFG_INST (
420
    .I(CLK0_BUF),
421
    .O(CLKFB_IN)
422
);
423
 
424
// synopsys translate_off
425
defparam dcm_adv_clk_main.CLK_FEEDBACK          = "1X";
426
defparam dcm_adv_clk_main.CLKDV_DIVIDE          = 2.5;
427
defparam dcm_adv_clk_main.CLKFX_DIVIDE          = 1;
428
defparam dcm_adv_clk_main.CLKFX_MULTIPLY        = 4;
429
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2     = "FALSE";
430
defparam dcm_adv_clk_main.CLKIN_PERIOD          = 20.000;
431
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT    = "NONE";
432
defparam dcm_adv_clk_main.DESKEW_ADJUST         = "SYSTEM_SYNCHRONOUS";
433
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE    = "LOW";
434
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE    = "LOW";
435
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
436
defparam dcm_adv_clk_main.FACTORY_JF            = 16'h8080;
437
defparam dcm_adv_clk_main.PHASE_SHIFT           = 0;
438
defparam dcm_adv_clk_main.STARTUP_WAIT          = "FALSE";
439
// synopsys translate_on  
440
`endif
441
 
442
 
443
//wire    dcm_locked = 1'b1;
444
//wire      reset_n;
445
 
446
//reg     dcm_clk;
447
//always @(posedge clk_50M_in)
448
//  if (~reset_n) dcm_clk <= 1'b0;
449
//  else          dcm_clk <= ~dcm_clk;
450
 
451
 
452
// Clock buffers
453
//------------------------
454
BUFG  buf_sys_clock  (.O(clk_sys), .I(dcm_clk));
455
 
456
 
457
//=============================================================================
458
// 3)  RESET GENERATION & FPGA STARTUP
459
//=============================================================================
460
 
461
// Reset input buffer
462
IBUF   ibuf_reset_n   (.O(reset_pin), .I(BTN3));
463
wire reset_pin_n = ~reset_pin;
464
 
465
// Release the reset only, if the DCM is locked
466
assign  reset_n = reset_pin_n & dcm_locked;
467
 
468
//Include the startup device   
469
wire  gsr_tb;
470
wire  gts_tb;
471
STARTUP_SPARTAN3 xstartup (.CLK(clk_sys), .GSR(gsr_tb), .GTS(gts_tb));
472
 
473
 
474
//=============================================================================
475
// 4)  OPENMSP430
476
//=============================================================================
477
 
478
openMSP430 openMSP430_0 (
479
 
480
// OUTPUTs
481
    .aclk_en      (aclk_en),      // ACLK enable
482
    .dbg_freeze   (dbg_freeze),   // Freeze peripherals
483
    .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
484 37 olivier.gi
    .dmem_addr    (dmem_addr),    // Data Memory address
485
    .dmem_cen     (dmem_cen),     // Data Memory chip enable (low active)
486
    .dmem_din     (dmem_din),     // Data Memory data input
487
    .dmem_wen     (dmem_wen),     // Data Memory write enable (low active)
488 2 olivier.gi
    .irq_acc      (irq_acc),      // Interrupt request accepted (one-hot signal)
489
    .mclk         (mclk),         // Main system clock
490
    .per_addr     (per_addr),     // Peripheral address
491
    .per_din      (per_din),      // Peripheral data input
492
    .per_wen      (per_wen),      // Peripheral write enable (high active)
493
    .per_en       (per_en),       // Peripheral enable (high active)
494 37 olivier.gi
    .pmem_addr    (pmem_addr),    // Program Memory address
495
    .pmem_cen     (pmem_cen),     // Program Memory chip enable (low active)
496
    .pmem_din     (pmem_din),     // Program Memory data input (optional)
497
    .pmem_wen     (pmem_wen),     // Program Memory write enable (low active) (optional)
498 2 olivier.gi
    .puc          (puc),          // Main system reset
499
    .smclk_en     (smclk_en),     // SMCLK enable
500
 
501
// INPUTs
502
    .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
503
    .dco_clk      (clk_sys),      // Fast oscillator (fast clock)
504 37 olivier.gi
    .dmem_dout    (dmem_dout),    // Data Memory data output
505 2 olivier.gi
    .irq          (irq_bus),      // Maskable interrupts
506
    .lfxt_clk     (1'b0),         // Low frequency oscillator (typ 32kHz)
507
    .nmi          (nmi),          // Non-maskable interrupt (asynchronous)
508
    .per_dout     (per_dout),     // Peripheral data output
509 37 olivier.gi
    .pmem_dout    (pmem_dout),    // Program Memory data output
510
    .reset_n      (reset_n)       // Reset Pin (low active)
511 2 olivier.gi
);
512
 
513
 
514
//=============================================================================
515
// 5)  OPENMSP430 PERIPHERALS
516
//=============================================================================
517
 
518
//
519
// Digital I/O
520
//-------------------------------
521
 
522 37 olivier.gi
omsp_gpio #(.P1_EN(1),
523
            .P2_EN(1),
524
            .P3_EN(1),
525
            .P4_EN(0),
526
            .P5_EN(0),
527
            .P6_EN(0)) gpio_0 (
528 2 olivier.gi
 
529
// OUTPUTs
530
    .irq_port1    (irq_port1),     // Port 1 interrupt
531
    .irq_port2    (irq_port2),     // Port 2 interrupt
532
    .p1_dout      (p1_dout),       // Port 1 data output
533
    .p1_dout_en   (p1_dout_en),    // Port 1 data output enable
534
    .p1_sel       (p1_sel),        // Port 1 function select
535
    .p2_dout      (p2_dout),       // Port 2 data output
536
    .p2_dout_en   (p2_dout_en),    // Port 2 data output enable
537
    .p2_sel       (p2_sel),        // Port 2 function select
538
    .p3_dout      (p3_dout),       // Port 3 data output
539
    .p3_dout_en   (p3_dout_en),    // Port 3 data output enable
540
    .p3_sel       (p3_sel),        // Port 3 function select
541
    .p4_dout      (),              // Port 4 data output
542
    .p4_dout_en   (),              // Port 4 data output enable
543
    .p4_sel       (),              // Port 4 function select
544
    .p5_dout      (),              // Port 5 data output
545
    .p5_dout_en   (),              // Port 5 data output enable
546
    .p5_sel       (),              // Port 5 function select
547
    .p6_dout      (),              // Port 6 data output
548
    .p6_dout_en   (),              // Port 6 data output enable
549
    .p6_sel       (),              // Port 6 function select
550
    .per_dout     (per_dout_dio),  // Peripheral data output
551
 
552
// INPUTs
553
    .mclk         (mclk),          // Main system clock
554
    .p1_din       (p1_din),        // Port 1 data input
555
    .p2_din       (p2_din),        // Port 2 data input
556
    .p3_din       (p3_din),        // Port 3 data input
557
    .p4_din       (8'h00),         // Port 4 data input
558
    .p5_din       (8'h00),         // Port 5 data input
559
    .p6_din       (8'h00),         // Port 6 data input
560
    .per_addr     (per_addr),      // Peripheral address
561
    .per_din      (per_din),       // Peripheral data input
562
    .per_en       (per_en),        // Peripheral enable (high active)
563
    .per_wen      (per_wen),       // Peripheral write enable (high active)
564
    .puc          (puc)            // Main system reset
565
);
566
 
567
//
568
// Timer A
569
//----------------------------------------------
570
 
571 37 olivier.gi
omsp_timerA timerA_0 (
572 2 olivier.gi
 
573
// OUTPUTs
574
    .irq_ta0      (irq_ta0),       // Timer A interrupt: TACCR0
575
    .irq_ta1      (irq_ta1),       // Timer A interrupt: TAIV, TACCR1, TACCR2
576
    .per_dout     (per_dout_tA),   // Peripheral data output
577
    .ta_out0      (ta_out0),       // Timer A output 0
578
    .ta_out0_en   (ta_out0_en),    // Timer A output 0 enable
579
    .ta_out1      (ta_out1),       // Timer A output 1
580
    .ta_out1_en   (ta_out1_en),    // Timer A output 1 enable
581
    .ta_out2      (ta_out2),       // Timer A output 2
582
    .ta_out2_en   (ta_out2_en),    // Timer A output 2 enable
583
 
584
// INPUTs
585
    .aclk_en      (aclk_en),       // ACLK enable (from CPU)
586
    .dbg_freeze   (dbg_freeze),    // Freeze Timer A counter
587
    .inclk        (inclk),         // INCLK external timer clock (SLOW)
588
    .irq_ta0_acc  (irq_acc[9]),    // Interrupt request TACCR0 accepted
589
    .mclk         (mclk),          // Main system clock
590
    .per_addr     (per_addr),      // Peripheral address
591
    .per_din      (per_din),       // Peripheral data input
592
    .per_en       (per_en),        // Peripheral enable (high active)
593
    .per_wen      (per_wen),       // Peripheral write enable (high active)
594
    .puc          (puc),           // Main system reset
595
    .smclk_en     (smclk_en),      // SMCLK enable (from CPU)
596
    .ta_cci0a     (ta_cci0a),      // Timer A capture 0 input A
597
    .ta_cci0b     (ta_cci0b),      // Timer A capture 0 input B
598
    .ta_cci1a     (ta_cci1a),      // Timer A capture 1 input A
599
    .ta_cci1b     (1'b0),          // Timer A capture 1 input B
600
    .ta_cci2a     (ta_cci2a),      // Timer A capture 2 input A
601
    .ta_cci2b     (1'b0),          // Timer A capture 2 input B
602
    .taclk        (taclk)          // TACLK external timer clock (SLOW)
603
);
604
 
605
 
606
//
607
// Four-Digit, Seven-Segment LED Display driver
608
//----------------------------------------------
609
 
610
driver_7segment driver_7segment_0 (
611
 
612
// OUTPUTs
613
    .per_dout     (per_dout_7seg), // Peripheral data output
614
    .seg_a        (seg_a_),        // Segment A control
615
    .seg_b        (seg_b_),        // Segment B control
616
    .seg_c        (seg_c_),        // Segment C control
617
    .seg_d        (seg_d_),        // Segment D control
618
    .seg_e        (seg_e_),        // Segment E control
619
    .seg_f        (seg_f_),        // Segment F control
620
    .seg_g        (seg_g_),        // Segment G control
621
    .seg_dp       (seg_dp_),       // Segment DP control
622
    .seg_an0      (seg_an0_),      // Anode 0 control
623
    .seg_an1      (seg_an1_),      // Anode 1 control
624
    .seg_an2      (seg_an2_),      // Anode 2 control
625
    .seg_an3      (seg_an3_),      // Anode 3 control
626
 
627
// INPUTs
628
    .mclk         (mclk),          // Main system clock
629
    .per_addr     (per_addr),      // Peripheral address
630
    .per_din      (per_din),       // Peripheral data input
631
    .per_en       (per_en),        // Peripheral enable (high active)
632
    .per_wen      (per_wen),       // Peripheral write enable (high active)
633
    .puc          (puc)            // Main system reset
634
);
635
 
636
 
637
//
638
// Combine peripheral data buses
639
//-------------------------------
640
 
641
assign per_dout = per_dout_dio  |
642
                  per_dout_tA   |
643
                  per_dout_7seg;
644
 
645
//
646
// Assign interrupts
647
//-------------------------------
648
 
649
assign nmi        =  1'b0;
650
assign irq_bus    = {1'b0,         // Vector 13  (0xFFFA)
651
                     1'b0,         // Vector 12  (0xFFF8)
652
                     1'b0,         // Vector 11  (0xFFF6)
653
                     1'b0,         // Vector 10  (0xFFF4) - Watchdog -
654
                     irq_ta0,      // Vector  9  (0xFFF2)
655
                     irq_ta1,      // Vector  8  (0xFFF0)
656
                     1'b0,         // Vector  7  (0xFFEE)
657
                     1'b0,         // Vector  6  (0xFFEC)
658
                     1'b0,         // Vector  5  (0xFFEA)
659
                     1'b0,         // Vector  4  (0xFFE8)
660
                     irq_port2,    // Vector  3  (0xFFE6)
661
                     irq_port1,    // Vector  2  (0xFFE4)
662
                     1'b0,         // Vector  1  (0xFFE2)
663
                     1'b0};        // Vector  0  (0xFFE0)
664
 
665
//
666
// GPIO Function selection
667
//--------------------------
668
 
669
// P1.0/TACLK      I/O pin / Timer_A, clock signal TACLK input
670
// P1.1/TA0        I/O pin / Timer_A, capture: CCI0A input, compare: Out0 output
671
// P1.2/TA1        I/O pin / Timer_A, capture: CCI1A input, compare: Out1 output
672
// P1.3/TA2        I/O pin / Timer_A, capture: CCI2A input, compare: Out2 output
673
// P1.4/SMCLK      I/O pin / SMCLK signal output
674
// P1.5/TA0        I/O pin / Timer_A, compare: Out0 output
675
// P1.6/TA1        I/O pin / Timer_A, compare: Out1 output
676
// P1.7/TA2        I/O pin / Timer_A, compare: Out2 output
677
wire [7:0] p1_io_mux_b_unconnected;
678
wire [7:0] p1_io_dout;
679
wire [7:0] p1_io_dout_en;
680
wire [7:0] p1_io_din;
681
 
682
io_mux #8 io_mux_p1 (
683
                     .a_din      (p1_din),
684
                     .a_dout     (p1_dout),
685
                     .a_dout_en  (p1_dout_en),
686
 
687
                     .b_din      ({p1_io_mux_b_unconnected[7],
688
                                   p1_io_mux_b_unconnected[6],
689
                                   p1_io_mux_b_unconnected[5],
690
                                   p1_io_mux_b_unconnected[4],
691
                                   ta_cci2a,
692
                                   ta_cci1a,
693
                                   ta_cci0a,
694
                                   taclk
695
                                  }),
696
                     .b_dout     ({ta_out2,
697
                                   ta_out1,
698
                                   ta_out0,
699
                                   (smclk_en & mclk),
700
                                   ta_out2,
701
                                   ta_out1,
702
                                   ta_out0,
703
                                   1'b0
704
                                  }),
705
                     .b_dout_en  ({ta_out2_en,
706
                                   ta_out1_en,
707
                                   ta_out0_en,
708
                                   1'b1,
709
                                   ta_out2_en,
710
                                   ta_out1_en,
711
                                   ta_out0_en,
712
                                   1'b0
713
                                  }),
714
 
715
                     .io_din     (p1_io_din),
716
                     .io_dout    (p1_io_dout),
717
                     .io_dout_en (p1_io_dout_en),
718
 
719
                     .sel        (p1_sel)
720
);
721
 
722
 
723
 
724
// P2.0/ACLK       I/O pin / ACLK output
725
// P2.1/INCLK      I/O pin / Timer_A, clock signal at INCLK
726
// P2.2/TA0        I/O pin / Timer_A, capture: CCI0B input
727
// P2.3/TA1        I/O pin / Timer_A, compare: Out1 output
728
// P2.4/TA2        I/O pin / Timer_A, compare: Out2 output
729
wire [7:0] p2_io_mux_b_unconnected;
730
wire [7:0] p2_io_dout;
731
wire [7:0] p2_io_dout_en;
732
wire [7:0] p2_io_din;
733
 
734
io_mux #8 io_mux_p2 (
735
                     .a_din      (p2_din),
736
                     .a_dout     (p2_dout),
737
                     .a_dout_en  (p2_dout_en),
738
 
739
                     .b_din      ({p2_io_mux_b_unconnected[7],
740
                                   p2_io_mux_b_unconnected[6],
741
                                   p2_io_mux_b_unconnected[5],
742
                                   p2_io_mux_b_unconnected[4],
743
                                   p2_io_mux_b_unconnected[3],
744
                                   ta_cci0b,
745
                                   inclk,
746
                                   p2_io_mux_b_unconnected[0]
747
                                  }),
748
                     .b_dout     ({1'b0,
749
                                   1'b0,
750
                                   1'b0,
751
                                   ta_out2,
752
                                   ta_out1,
753
                                   1'b0,
754
                                   1'b0,
755
                                   (aclk_en & mclk)
756
                                  }),
757
                     .b_dout_en  ({1'b0,
758
                                   1'b0,
759
                                   1'b0,
760
                                   ta_out2_en,
761
                                   ta_out1_en,
762
                                   1'b0,
763
                                   1'b0,
764
                                   1'b1
765
                                  }),
766
 
767
                     .io_din     (p2_io_din),
768
                     .io_dout    (p2_io_dout),
769
                     .io_dout_en (p2_io_dout_en),
770
 
771
                     .sel        (p2_sel)
772
);
773
 
774
 
775
//=============================================================================
776 37 olivier.gi
// 6)  PROGRAM AND DATA MEMORIES
777 2 olivier.gi
//=============================================================================
778
 
779 37 olivier.gi
// Data Memory
780 2 olivier.gi
ram_8x512_hi ram_8x512_hi_0 (
781 37 olivier.gi
    .addr         (dmem_addr),
782 2 olivier.gi
    .clk          (clk_sys),
783 37 olivier.gi
    .din          (dmem_din[15:8]),
784
    .dout         (dmem_dout[15:8]),
785
    .en           (dmem_cen),
786
    .we           (dmem_wen[1])
787 2 olivier.gi
);
788
ram_8x512_lo ram_8x512_lo_0 (
789 37 olivier.gi
    .addr         (dmem_addr),
790 2 olivier.gi
    .clk          (clk_sys),
791 37 olivier.gi
    .din          (dmem_din[7:0]),
792
    .dout         (dmem_dout[7:0]),
793
    .en           (dmem_cen),
794
    .we           (dmem_wen[0])
795 2 olivier.gi
);
796
 
797
 
798 37 olivier.gi
// Program Memory
799 2 olivier.gi
rom_8x2k_hi rom_8x2k_hi_0 (
800 37 olivier.gi
    .addr         (pmem_addr),
801 2 olivier.gi
    .clk          (clk_sys),
802 37 olivier.gi
    .din          (pmem_din[15:8]),
803
    .dout         (pmem_dout[15:8]),
804
    .en           (pmem_cen),
805
    .we           (pmem_wen[1])
806 2 olivier.gi
);
807
 
808
rom_8x2k_lo rom_8x2k_lo_0 (
809 37 olivier.gi
    .addr         (pmem_addr),
810 2 olivier.gi
    .clk          (clk_sys),
811 37 olivier.gi
    .din          (pmem_din[7:0]),
812
    .dout         (pmem_dout[7:0]),
813
    .en           (pmem_cen),
814
    .we           (pmem_wen[0])
815 2 olivier.gi
);
816
 
817
 
818
 
819
//=============================================================================
820
// 7)  I/O CELLS
821
//=============================================================================
822
 
823
 
824
// Slide Switches (Port 1 inputs)
825
//--------------------------------
826
IBUF  SW7_PIN        (.O(p3_din[7]),                   .I(SW7));
827
IBUF  SW6_PIN        (.O(p3_din[6]),                   .I(SW6));
828
IBUF  SW5_PIN        (.O(p3_din[5]),                   .I(SW5));
829
IBUF  SW4_PIN        (.O(p3_din[4]),                   .I(SW4));
830
IBUF  SW3_PIN        (.O(p3_din[3]),                   .I(SW3));
831
IBUF  SW2_PIN        (.O(p3_din[2]),                   .I(SW2));
832
IBUF  SW1_PIN        (.O(p3_din[1]),                   .I(SW1));
833
IBUF  SW0_PIN        (.O(p3_din[0]),                   .I(SW0));
834
 
835
// LEDs (Port 1 outputs)
836
//-----------------------
837
OBUF  LED7_PIN       (.I(p3_dout[7] & p3_dout_en[7]),  .O(LED7));
838
OBUF  LED6_PIN       (.I(p3_dout[6] & p3_dout_en[6]),  .O(LED6));
839
OBUF  LED5_PIN       (.I(p3_dout[5] & p3_dout_en[5]),  .O(LED5));
840
OBUF  LED4_PIN       (.I(p3_dout[4] & p3_dout_en[4]),  .O(LED4));
841
OBUF  LED3_PIN       (.I(p3_dout[3] & p3_dout_en[3]),  .O(LED3));
842
OBUF  LED2_PIN       (.I(p3_dout[2] & p3_dout_en[2]),  .O(LED2));
843
OBUF  LED1_PIN       (.I(p3_dout[1] & p3_dout_en[1]),  .O(LED1));
844
OBUF  LED0_PIN       (.I(p3_dout[0] & p3_dout_en[0]),  .O(LED0));
845
 
846
// Push Button Switches
847
//----------------------
848
IBUF  BTN2_PIN       (.O(),                            .I(BTN2));
849
IBUF  BTN1_PIN       (.O(),                            .I(BTN1));
850
IBUF  BTN0_PIN       (.O(),                            .I(BTN0));
851
 
852
// Four-Sigit, Seven-Segment LED Display
853
//---------------------------------------
854
OBUF  SEG_A_PIN      (.I(seg_a_),                      .O(SEG_A));
855
OBUF  SEG_B_PIN      (.I(seg_b_),                      .O(SEG_B));
856
OBUF  SEG_C_PIN      (.I(seg_c_),                      .O(SEG_C));
857
OBUF  SEG_D_PIN      (.I(seg_d_),                      .O(SEG_D));
858
OBUF  SEG_E_PIN      (.I(seg_e_),                      .O(SEG_E));
859
OBUF  SEG_F_PIN      (.I(seg_f_),                      .O(SEG_F));
860
OBUF  SEG_G_PIN      (.I(seg_g_),                      .O(SEG_G));
861
OBUF  SEG_DP_PIN     (.I(seg_dp_),                     .O(SEG_DP));
862
OBUF  SEG_AN0_PIN    (.I(seg_an0_),                    .O(SEG_AN0));
863
OBUF  SEG_AN1_PIN    (.I(seg_an1_),                    .O(SEG_AN1));
864
OBUF  SEG_AN2_PIN    (.I(seg_an2_),                    .O(SEG_AN2));
865
OBUF  SEG_AN3_PIN    (.I(seg_an3_),                    .O(SEG_AN3));
866
 
867
// RS-232 Port
868
//----------------------
869
// P1.1 (TX) and P2.2 (RX)
870
assign p1_io_din      = 8'h00;
871
assign p2_io_din[7:3] = 5'h00;
872
assign p2_io_din[1:0] = 2'h0;
873
 
874
// Mux the RS-232 port between IO port and the debug interface.
875
// The mux is controlled with the SW0 switch
876
wire   uart_txd_out = p3_din[0] ? dbg_uart_txd : p1_io_dout[1];
877
wire   uart_rxd_in;
878
assign p2_io_din[2] = p3_din[0] ? 1'b1         : uart_rxd_in;
879
assign dbg_uart_rxd = p3_din[0] ? uart_rxd_in  : 1'b1;
880
 
881
IBUF  UART_RXD_PIN   (.O(uart_rxd_in),                 .I(UART_RXD));
882
OBUF  UART_TXD_PIN   (.I(uart_txd_out),                .O(UART_TXD));
883
 
884
IBUF  UART_RXD_A_PIN (.O(),                            .I(UART_RXD_A));
885
OBUF  UART_TXD_A_PIN (.I(1'b0),                        .O(UART_TXD_A));
886
 
887
 
888
// PS/2 Mouse/Keyboard Port
889
//--------------------------
890
IOBUF PS2_D_PIN      (.O(), .I(1'b0), .T(1'b1),        .IO(PS2_D));
891
OBUF  PS2_C_PIN      (.I(1'b0),                        .O(PS2_C));
892
 
893
// Fast, Asynchronous SRAM
894
//--------------------------
895
OBUF  SRAM_A17_PIN   (.I(1'b0),                        .O(SRAM_A17));
896
OBUF  SRAM_A16_PIN   (.I(1'b0),                        .O(SRAM_A16));
897
OBUF  SRAM_A15_PIN   (.I(1'b0),                        .O(SRAM_A15));
898
OBUF  SRAM_A14_PIN   (.I(1'b0),                        .O(SRAM_A14));
899
OBUF  SRAM_A13_PIN   (.I(1'b0),                        .O(SRAM_A13));
900
OBUF  SRAM_A12_PIN   (.I(1'b0),                        .O(SRAM_A12));
901
OBUF  SRAM_A11_PIN   (.I(1'b0),                        .O(SRAM_A11));
902
OBUF  SRAM_A10_PIN   (.I(1'b0),                        .O(SRAM_A10));
903
OBUF  SRAM_A9_PIN    (.I(1'b0),                        .O(SRAM_A9));
904
OBUF  SRAM_A8_PIN    (.I(1'b0),                        .O(SRAM_A8));
905
OBUF  SRAM_A7_PIN    (.I(1'b0),                        .O(SRAM_A7));
906
OBUF  SRAM_A6_PIN    (.I(1'b0),                        .O(SRAM_A6));
907
OBUF  SRAM_A5_PIN    (.I(1'b0),                        .O(SRAM_A5));
908
OBUF  SRAM_A4_PIN    (.I(1'b0),                        .O(SRAM_A4));
909
OBUF  SRAM_A3_PIN    (.I(1'b0),                        .O(SRAM_A3));
910
OBUF  SRAM_A2_PIN    (.I(1'b0),                        .O(SRAM_A2));
911
OBUF  SRAM_A1_PIN    (.I(1'b0),                        .O(SRAM_A1));
912
OBUF  SRAM_A0_PIN    (.I(1'b0),                        .O(SRAM_A0));
913
OBUF  SRAM_OE_PIN    (.I(1'b1),                        .O(SRAM_OE));
914
OBUF  SRAM_WE_PIN    (.I(1'b1),                        .O(SRAM_WE));
915
IOBUF SRAM0_IO15_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO15));
916
IOBUF SRAM0_IO14_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO14));
917
IOBUF SRAM0_IO13_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO13));
918
IOBUF SRAM0_IO12_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO12));
919
IOBUF SRAM0_IO11_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO11));
920
IOBUF SRAM0_IO10_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO10));
921
IOBUF SRAM0_IO9_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO9));
922
IOBUF SRAM0_IO8_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO8));
923
IOBUF SRAM0_IO7_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO7));
924
IOBUF SRAM0_IO6_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO6));
925
IOBUF SRAM0_IO5_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO5));
926
IOBUF SRAM0_IO4_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO4));
927
IOBUF SRAM0_IO3_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO3));
928
IOBUF SRAM0_IO2_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO2));
929
IOBUF SRAM0_IO1_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO1));
930
IOBUF SRAM0_IO0_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM0_IO0));
931
OBUF  SRAM0_CE1_PIN  (.I(1'b1),                        .O(SRAM0_CE1));
932
OBUF  SRAM0_UB1_PIN  (.I(1'b1),                        .O(SRAM0_UB1));
933
OBUF  SRAM0_LB1_PIN  (.I(1'b1),                        .O(SRAM0_LB1));
934
IOBUF SRAM1_IO15_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO15));
935
IOBUF SRAM1_IO14_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO14));
936
IOBUF SRAM1_IO13_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO13));
937
IOBUF SRAM1_IO12_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO12));
938
IOBUF SRAM1_IO11_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO11));
939
IOBUF SRAM1_IO10_PIN (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO10));
940
IOBUF SRAM1_IO9_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO9));
941
IOBUF SRAM1_IO8_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO8));
942
IOBUF SRAM1_IO7_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO7));
943
IOBUF SRAM1_IO6_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO6));
944
IOBUF SRAM1_IO5_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO5));
945
IOBUF SRAM1_IO4_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO4));
946
IOBUF SRAM1_IO3_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO3));
947
IOBUF SRAM1_IO2_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO2));
948
IOBUF SRAM1_IO1_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO1));
949
IOBUF SRAM1_IO0_PIN  (.O(), .I(1'b0), .T(1'b1),        .IO(SRAM1_IO0));
950
OBUF  SRAM1_CE2_PIN  (.I(1'b1),                        .O(SRAM1_CE2));
951
OBUF  SRAM1_UB2_PIN  (.I(1'b1),                        .O(SRAM1_UB2));
952
OBUF  SRAM1_LB2_PIN  (.I(1'b1),                        .O(SRAM1_LB2));
953
 
954
// VGA Port
955
//---------------------------------------
956
OBUF  VGA_R_PIN      (.I(1'b0),                        .O(VGA_R));
957
OBUF  VGA_G_PIN      (.I(1'b0),                        .O(VGA_G));
958
OBUF  VGA_B_PIN      (.I(1'b0),                        .O(VGA_B));
959
OBUF  VGA_HS_PIN     (.I(1'b0),                        .O(VGA_HS));
960
OBUF  VGA_VS_PIN     (.I(1'b0),                        .O(VGA_VS));
961
 
962
 
963
endmodule // openMSP430_fpga
964
 

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