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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430_fpga.v
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//
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// *Module Description:
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// openMSP430 FPGA Top-level for the Diligent
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// Spartan-3 starter kit.
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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olivier.gi |
// $Rev: 155 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-10-15 23:35:05 +0200 (Mon, 15 Oct 2012) $
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//----------------------------------------------------------------------------
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olivier.gi |
`include "openMSP430_defines.v"
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2 |
olivier.gi |
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module openMSP430_fpga (
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// Clock Sources
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CLK_50MHz,
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CLK_SOCKET,
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// Slide Switches
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SW7,
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SW6,
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SW5,
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SW4,
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SW3,
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SW2,
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SW1,
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SW0,
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// Push Button Switches
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BTN3,
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BTN2,
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BTN1,
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BTN0,
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// LEDs
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LED7,
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LED6,
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LED5,
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LED4,
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LED3,
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LED2,
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LED1,
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LED0,
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// Four-Sigit, Seven-Segment LED Display
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SEG_A,
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SEG_B,
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SEG_C,
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SEG_D,
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SEG_E,
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SEG_F,
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SEG_G,
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SEG_DP,
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SEG_AN0,
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SEG_AN1,
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SEG_AN2,
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SEG_AN3,
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// RS-232 Port
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UART_RXD,
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UART_TXD,
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UART_RXD_A,
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UART_TXD_A,
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// PS/2 Mouse/Keyboard Port
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PS2_D,
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PS2_C,
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// Fast, Asynchronous SRAM
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SRAM_A17, // Address Bus Connections
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SRAM_A16,
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SRAM_A15,
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SRAM_A14,
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SRAM_A13,
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SRAM_A12,
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SRAM_A11,
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SRAM_A10,
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SRAM_A9,
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SRAM_A8,
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SRAM_A7,
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SRAM_A6,
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SRAM_A5,
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SRAM_A4,
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SRAM_A3,
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SRAM_A2,
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SRAM_A1,
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SRAM_A0,
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SRAM_OE, // Write enable and output enable control signals
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SRAM_WE,
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SRAM0_IO15, // SRAM Data signals, chip enables, and byte enables
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SRAM0_IO14,
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SRAM0_IO13,
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SRAM0_IO12,
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SRAM0_IO11,
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SRAM0_IO10,
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SRAM0_IO9,
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SRAM0_IO8,
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SRAM0_IO7,
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SRAM0_IO6,
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SRAM0_IO5,
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SRAM0_IO4,
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SRAM0_IO3,
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SRAM0_IO2,
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SRAM0_IO1,
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SRAM0_IO0,
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SRAM0_CE1,
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SRAM0_UB1,
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SRAM0_LB1,
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SRAM1_IO15,
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SRAM1_IO14,
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SRAM1_IO13,
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SRAM1_IO12,
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SRAM1_IO11,
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SRAM1_IO10,
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SRAM1_IO9,
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SRAM1_IO8,
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SRAM1_IO7,
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SRAM1_IO6,
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SRAM1_IO5,
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SRAM1_IO4,
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SRAM1_IO3,
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SRAM1_IO2,
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SRAM1_IO1,
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SRAM1_IO0,
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SRAM1_CE2,
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SRAM1_UB2,
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SRAM1_LB2,
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// VGA Port
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VGA_R,
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VGA_G,
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VGA_B,
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VGA_HS,
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VGA_VS
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);
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// Clock Sources
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input CLK_50MHz;
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input CLK_SOCKET;
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// Slide Switches
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input SW7;
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input SW6;
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input SW5;
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input SW4;
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input SW3;
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input SW2;
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input SW1;
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input SW0;
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// Push Button Switches
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input BTN3;
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input BTN2;
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input BTN1;
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input BTN0;
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// LEDs
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output LED7;
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output LED6;
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output LED5;
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output LED4;
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output LED3;
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output LED2;
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output LED1;
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output LED0;
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// Four-Sigit, Seven-Segment LED Display
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output SEG_A;
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output SEG_B;
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output SEG_C;
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output SEG_D;
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output SEG_E;
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output SEG_F;
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output SEG_G;
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output SEG_DP;
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output SEG_AN0;
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output SEG_AN1;
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output SEG_AN2;
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output SEG_AN3;
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// RS-232 Port
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input UART_RXD;
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output UART_TXD;
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input UART_RXD_A;
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output UART_TXD_A;
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// PS/2 Mouse/Keyboard Port
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inout PS2_D;
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output PS2_C;
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// Fast, Asynchronous SRAM
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output SRAM_A17; // Address Bus Connections
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output SRAM_A16;
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output SRAM_A15;
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output SRAM_A14;
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output SRAM_A13;
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output SRAM_A12;
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output SRAM_A11;
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output SRAM_A10;
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output SRAM_A9;
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output SRAM_A8;
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output SRAM_A7;
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output SRAM_A6;
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output SRAM_A5;
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output SRAM_A4;
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output SRAM_A3;
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output SRAM_A2;
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output SRAM_A1;
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output SRAM_A0;
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output SRAM_OE; // Write enable and output enable control signals
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output SRAM_WE;
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inout SRAM0_IO15; // SRAM Data signals, chip enables, and byte enables
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inout SRAM0_IO14;
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inout SRAM0_IO13;
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inout SRAM0_IO12;
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inout SRAM0_IO11;
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inout SRAM0_IO10;
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inout SRAM0_IO9;
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inout SRAM0_IO8;
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inout SRAM0_IO7;
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inout SRAM0_IO6;
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inout SRAM0_IO5;
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inout SRAM0_IO4;
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inout SRAM0_IO3;
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inout SRAM0_IO2;
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inout SRAM0_IO1;
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inout SRAM0_IO0;
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output SRAM0_CE1;
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output SRAM0_UB1;
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output SRAM0_LB1;
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inout SRAM1_IO15;
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inout SRAM1_IO14;
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inout SRAM1_IO13;
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inout SRAM1_IO12;
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inout SRAM1_IO11;
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inout SRAM1_IO10;
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inout SRAM1_IO9;
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inout SRAM1_IO8;
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inout SRAM1_IO7;
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inout SRAM1_IO6;
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inout SRAM1_IO5;
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inout SRAM1_IO4;
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inout SRAM1_IO3;
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inout SRAM1_IO2;
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inout SRAM1_IO1;
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inout SRAM1_IO0;
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output SRAM1_CE2;
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output SRAM1_UB2;
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output SRAM1_LB2;
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// VGA Port
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output VGA_R;
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output VGA_G;
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output VGA_B;
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output VGA_HS;
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output VGA_VS;
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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// openMSP430 output buses
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292 |
111 |
olivier.gi |
wire [13:0] per_addr;
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293 |
37 |
olivier.gi |
wire [15:0] per_din;
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294 |
109 |
olivier.gi |
wire [1:0] per_we;
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37 |
olivier.gi |
wire [`DMEM_MSB:0] dmem_addr;
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wire [15:0] dmem_din;
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wire [1:0] dmem_wen;
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wire [`PMEM_MSB:0] pmem_addr;
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wire [15:0] pmem_din;
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wire [1:0] pmem_wen;
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wire [13:0] irq_acc;
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2 |
olivier.gi |
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// openMSP430 input buses
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37 |
olivier.gi |
wire [13:0] irq_bus;
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wire [15:0] per_dout;
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wire [15:0] dmem_dout;
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wire [15:0] pmem_dout;
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2 |
olivier.gi |
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// GPIO
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310 |
37 |
olivier.gi |
wire [7:0] p1_din;
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wire [7:0] p1_dout;
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wire [7:0] p1_dout_en;
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wire [7:0] p1_sel;
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wire [7:0] p2_din;
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wire [7:0] p2_dout;
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wire [7:0] p2_dout_en;
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wire [7:0] p2_sel;
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wire [7:0] p3_din;
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wire [7:0] p3_dout;
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wire [7:0] p3_dout_en;
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wire [7:0] p3_sel;
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wire [15:0] per_dout_dio;
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2 |
olivier.gi |
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// Timer A
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325 |
37 |
olivier.gi |
wire [15:0] per_dout_tA;
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326 |
2 |
olivier.gi |
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// 7 segment driver
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328 |
37 |
olivier.gi |
wire [15:0] per_dout_7seg;
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329 |
2 |
olivier.gi |
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330 |
136 |
olivier.gi |
// Simple UART
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331 |
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wire irq_uart_rx;
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332 |
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wire irq_uart_tx;
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333 |
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wire [15:0] per_dout_uart;
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334 |
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wire hw_uart_txd;
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335 |
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wire hw_uart_rxd;
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336 |
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337 |
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338 |
2 |
olivier.gi |
// Others
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339 |
37 |
olivier.gi |
wire reset_pin;
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340 |
2 |
olivier.gi |
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341 |
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342 |
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//=============================================================================
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343 |
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// 2) CLOCK GENERATION
|
344 |
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//=============================================================================
|
345 |
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346 |
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// Input buffers
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347 |
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//------------------------
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348 |
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IBUFG ibuf_clk_main (.O(clk_50M_in), .I(CLK_50MHz));
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349 |
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IBUFG ibuf_clk_socket (.O(clk_socket_in), .I(CLK_SOCKET));
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350 |
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351 |
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352 |
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// Digital Clock Manager
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353 |
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//------------------------
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354 |
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355 |
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// Generate 20MHz clock from 50MHz on-board oscillator
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356 |
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//`define DCM_FX_MODE
|
357 |
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`ifdef DCM_FX_MODE
|
358 |
|
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DCM dcm_adv_clk_main (
|
359 |
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|
360 |
|
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// OUTPUTs
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361 |
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.CLK0 (),
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362 |
|
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.CLK90 (),
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363 |
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.CLK180 (),
|
364 |
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.CLK270 (),
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365 |
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.CLK2X (),
|
366 |
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.CLK2X180 (),
|
367 |
|
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.CLKDV (),
|
368 |
|
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.CLKFX (dcm_clk),
|
369 |
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.CLKFX180 (),
|
370 |
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.PSDONE (),
|
371 |
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.STATUS (),
|
372 |
|
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.LOCKED (dcm_locked),
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373 |
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|
374 |
|
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// INPUTs
|
375 |
|
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.CLKIN (clk_50M_in),
|
376 |
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.CLKFB (1'b0),
|
377 |
|
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.PSINCDEC (1'b0),
|
378 |
|
|
.PSEN (1'b0),
|
379 |
|
|
.DSSEN (1'b0),
|
380 |
|
|
.RST (reset_pin),
|
381 |
|
|
.PSCLK (1'b0)
|
382 |
|
|
);
|
383 |
|
|
|
384 |
|
|
// synopsys translate_off
|
385 |
|
|
defparam dcm_adv_clk_main.CLK_FEEDBACK = "NONE";
|
386 |
|
|
defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5;
|
387 |
|
|
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE";
|
388 |
|
|
defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.0;
|
389 |
|
|
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE";
|
390 |
|
|
defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
391 |
|
|
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW";
|
392 |
|
|
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW";
|
393 |
|
|
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
|
394 |
|
|
defparam dcm_adv_clk_main.FACTORY_JF = 16'hC080;
|
395 |
|
|
defparam dcm_adv_clk_main.PHASE_SHIFT = 0;
|
396 |
|
|
defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE";
|
397 |
|
|
|
398 |
|
|
defparam dcm_adv_clk_main.CLKFX_DIVIDE = 5;
|
399 |
|
|
defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 2;
|
400 |
|
|
// synopsys translate_on
|
401 |
|
|
`else
|
402 |
|
|
DCM dcm_adv_clk_main (
|
403 |
|
|
|
404 |
|
|
// OUTPUTs
|
405 |
|
|
.CLKDV (dcm_clk),
|
406 |
|
|
.CLKFX (),
|
407 |
|
|
.CLKFX180 (),
|
408 |
|
|
.CLK0 (CLK0_BUF),
|
409 |
|
|
.CLK2X (),
|
410 |
|
|
.CLK2X180 (),
|
411 |
|
|
.CLK90 (),
|
412 |
|
|
.CLK180 (),
|
413 |
|
|
.CLK270 (),
|
414 |
|
|
.LOCKED (dcm_locked),
|
415 |
|
|
.PSDONE (),
|
416 |
|
|
.STATUS (),
|
417 |
|
|
|
418 |
|
|
// INPUTs
|
419 |
|
|
.CLKFB (CLKFB_IN),
|
420 |
|
|
.CLKIN (clk_50M_in),
|
421 |
|
|
.PSEN (1'b0),
|
422 |
|
|
.PSINCDEC (1'b0),
|
423 |
|
|
.DSSEN (1'b0),
|
424 |
|
|
.PSCLK (1'b0),
|
425 |
|
|
.RST (reset_pin)
|
426 |
|
|
);
|
427 |
|
|
BUFG CLK0_BUFG_INST (
|
428 |
|
|
.I(CLK0_BUF),
|
429 |
|
|
.O(CLKFB_IN)
|
430 |
|
|
);
|
431 |
|
|
|
432 |
|
|
// synopsys translate_off
|
433 |
|
|
defparam dcm_adv_clk_main.CLK_FEEDBACK = "1X";
|
434 |
|
|
defparam dcm_adv_clk_main.CLKDV_DIVIDE = 2.5;
|
435 |
|
|
defparam dcm_adv_clk_main.CLKFX_DIVIDE = 1;
|
436 |
|
|
defparam dcm_adv_clk_main.CLKFX_MULTIPLY = 4;
|
437 |
|
|
defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2 = "FALSE";
|
438 |
|
|
defparam dcm_adv_clk_main.CLKIN_PERIOD = 20.000;
|
439 |
|
|
defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT = "NONE";
|
440 |
|
|
defparam dcm_adv_clk_main.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
441 |
|
|
defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE = "LOW";
|
442 |
|
|
defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE = "LOW";
|
443 |
|
|
defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";
|
444 |
|
|
defparam dcm_adv_clk_main.FACTORY_JF = 16'h8080;
|
445 |
|
|
defparam dcm_adv_clk_main.PHASE_SHIFT = 0;
|
446 |
|
|
defparam dcm_adv_clk_main.STARTUP_WAIT = "FALSE";
|
447 |
|
|
// synopsys translate_on
|
448 |
|
|
`endif
|
449 |
|
|
|
450 |
|
|
|
451 |
|
|
//wire dcm_locked = 1'b1;
|
452 |
|
|
//wire reset_n;
|
453 |
|
|
|
454 |
|
|
//reg dcm_clk;
|
455 |
|
|
//always @(posedge clk_50M_in)
|
456 |
|
|
// if (~reset_n) dcm_clk <= 1'b0;
|
457 |
|
|
// else dcm_clk <= ~dcm_clk;
|
458 |
|
|
|
459 |
|
|
|
460 |
|
|
// Clock buffers
|
461 |
|
|
//------------------------
|
462 |
|
|
BUFG buf_sys_clock (.O(clk_sys), .I(dcm_clk));
|
463 |
|
|
|
464 |
|
|
|
465 |
|
|
//=============================================================================
|
466 |
|
|
// 3) RESET GENERATION & FPGA STARTUP
|
467 |
|
|
//=============================================================================
|
468 |
|
|
|
469 |
|
|
// Reset input buffer
|
470 |
|
|
IBUF ibuf_reset_n (.O(reset_pin), .I(BTN3));
|
471 |
|
|
wire reset_pin_n = ~reset_pin;
|
472 |
|
|
|
473 |
|
|
// Release the reset only, if the DCM is locked
|
474 |
|
|
assign reset_n = reset_pin_n & dcm_locked;
|
475 |
|
|
|
476 |
|
|
//Include the startup device
|
477 |
|
|
wire gsr_tb;
|
478 |
|
|
wire gts_tb;
|
479 |
|
|
STARTUP_SPARTAN3 xstartup (.CLK(clk_sys), .GSR(gsr_tb), .GTS(gts_tb));
|
480 |
|
|
|
481 |
|
|
|
482 |
|
|
//=============================================================================
|
483 |
|
|
// 4) OPENMSP430
|
484 |
|
|
//=============================================================================
|
485 |
|
|
|
486 |
|
|
openMSP430 openMSP430_0 (
|
487 |
|
|
|
488 |
|
|
// OUTPUTs
|
489 |
155 |
olivier.gi |
.aclk (), // ASIC ONLY: ACLK
|
490 |
|
|
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
|
491 |
|
|
.dbg_freeze (dbg_freeze), // Freeze peripherals
|
492 |
|
|
.dbg_i2c_sda_out (), // Debug interface: I2C SDA OUT
|
493 |
|
|
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
|
494 |
|
|
.dco_enable (), // ASIC ONLY: Fast oscillator enable
|
495 |
|
|
.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
496 |
|
|
.dmem_addr (dmem_addr), // Data Memory address
|
497 |
|
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
498 |
|
|
.dmem_din (dmem_din), // Data Memory data input
|
499 |
|
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
500 |
|
|
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
|
501 |
|
|
.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
|
502 |
|
|
.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
503 |
|
|
.mclk (mclk), // Main system clock
|
504 |
|
|
.per_addr (per_addr), // Peripheral address
|
505 |
|
|
.per_din (per_din), // Peripheral data input
|
506 |
|
|
.per_we (per_we), // Peripheral write enable (high active)
|
507 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
508 |
|
|
.pmem_addr (pmem_addr), // Program Memory address
|
509 |
|
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
510 |
|
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
511 |
|
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
512 |
|
|
.puc_rst (puc_rst), // Main system reset
|
513 |
|
|
.smclk (), // ASIC ONLY: SMCLK
|
514 |
|
|
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
|
515 |
2 |
olivier.gi |
|
516 |
|
|
// INPUTs
|
517 |
155 |
olivier.gi |
.cpu_en (1'b1), // Enable CPU code execution (asynchronous and non-glitchy)
|
518 |
|
|
.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
|
519 |
|
|
.dbg_i2c_addr (7'h00), // Debug interface: I2C Address
|
520 |
|
|
.dbg_i2c_broadcast (7'h00), // Debug interface: I2C Broadcast Address (for multicore systems)
|
521 |
|
|
.dbg_i2c_scl (1'b1), // Debug interface: I2C SCL
|
522 |
|
|
.dbg_i2c_sda_in (1'b1), // Debug interface: I2C SDA IN
|
523 |
|
|
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
|
524 |
|
|
.dco_clk (clk_sys), // Fast oscillator (fast clock)
|
525 |
|
|
.dmem_dout (dmem_dout), // Data Memory data output
|
526 |
|
|
.irq (irq_bus), // Maskable interrupts
|
527 |
|
|
.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
|
528 |
|
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
529 |
|
|
.per_dout (per_dout), // Peripheral data output
|
530 |
|
|
.pmem_dout (pmem_dout), // Program Memory data output
|
531 |
|
|
.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
|
532 |
|
|
.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
|
533 |
|
|
.scan_mode (1'b0), // ASIC ONLY: Scan mode
|
534 |
|
|
.wkup (1'b0) // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
|
535 |
2 |
olivier.gi |
);
|
536 |
|
|
|
537 |
|
|
|
538 |
|
|
//=============================================================================
|
539 |
|
|
// 5) OPENMSP430 PERIPHERALS
|
540 |
|
|
//=============================================================================
|
541 |
|
|
|
542 |
|
|
//
|
543 |
|
|
// Digital I/O
|
544 |
|
|
//-------------------------------
|
545 |
|
|
|
546 |
37 |
olivier.gi |
omsp_gpio #(.P1_EN(1),
|
547 |
|
|
.P2_EN(1),
|
548 |
|
|
.P3_EN(1),
|
549 |
|
|
.P4_EN(0),
|
550 |
|
|
.P5_EN(0),
|
551 |
|
|
.P6_EN(0)) gpio_0 (
|
552 |
2 |
olivier.gi |
|
553 |
|
|
// OUTPUTs
|
554 |
|
|
.irq_port1 (irq_port1), // Port 1 interrupt
|
555 |
|
|
.irq_port2 (irq_port2), // Port 2 interrupt
|
556 |
|
|
.p1_dout (p1_dout), // Port 1 data output
|
557 |
|
|
.p1_dout_en (p1_dout_en), // Port 1 data output enable
|
558 |
|
|
.p1_sel (p1_sel), // Port 1 function select
|
559 |
|
|
.p2_dout (p2_dout), // Port 2 data output
|
560 |
|
|
.p2_dout_en (p2_dout_en), // Port 2 data output enable
|
561 |
|
|
.p2_sel (p2_sel), // Port 2 function select
|
562 |
|
|
.p3_dout (p3_dout), // Port 3 data output
|
563 |
|
|
.p3_dout_en (p3_dout_en), // Port 3 data output enable
|
564 |
|
|
.p3_sel (p3_sel), // Port 3 function select
|
565 |
|
|
.p4_dout (), // Port 4 data output
|
566 |
|
|
.p4_dout_en (), // Port 4 data output enable
|
567 |
|
|
.p4_sel (), // Port 4 function select
|
568 |
|
|
.p5_dout (), // Port 5 data output
|
569 |
|
|
.p5_dout_en (), // Port 5 data output enable
|
570 |
|
|
.p5_sel (), // Port 5 function select
|
571 |
|
|
.p6_dout (), // Port 6 data output
|
572 |
|
|
.p6_dout_en (), // Port 6 data output enable
|
573 |
|
|
.p6_sel (), // Port 6 function select
|
574 |
|
|
.per_dout (per_dout_dio), // Peripheral data output
|
575 |
|
|
|
576 |
|
|
// INPUTs
|
577 |
|
|
.mclk (mclk), // Main system clock
|
578 |
|
|
.p1_din (p1_din), // Port 1 data input
|
579 |
|
|
.p2_din (p2_din), // Port 2 data input
|
580 |
|
|
.p3_din (p3_din), // Port 3 data input
|
581 |
|
|
.p4_din (8'h00), // Port 4 data input
|
582 |
|
|
.p5_din (8'h00), // Port 5 data input
|
583 |
|
|
.p6_din (8'h00), // Port 6 data input
|
584 |
|
|
.per_addr (per_addr), // Peripheral address
|
585 |
|
|
.per_din (per_din), // Peripheral data input
|
586 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
587 |
109 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
588 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
589 |
2 |
olivier.gi |
);
|
590 |
|
|
|
591 |
|
|
//
|
592 |
|
|
// Timer A
|
593 |
|
|
//----------------------------------------------
|
594 |
|
|
|
595 |
37 |
olivier.gi |
omsp_timerA timerA_0 (
|
596 |
2 |
olivier.gi |
|
597 |
|
|
// OUTPUTs
|
598 |
|
|
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
|
599 |
|
|
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
|
600 |
|
|
.per_dout (per_dout_tA), // Peripheral data output
|
601 |
|
|
.ta_out0 (ta_out0), // Timer A output 0
|
602 |
|
|
.ta_out0_en (ta_out0_en), // Timer A output 0 enable
|
603 |
|
|
.ta_out1 (ta_out1), // Timer A output 1
|
604 |
|
|
.ta_out1_en (ta_out1_en), // Timer A output 1 enable
|
605 |
|
|
.ta_out2 (ta_out2), // Timer A output 2
|
606 |
|
|
.ta_out2_en (ta_out2_en), // Timer A output 2 enable
|
607 |
|
|
|
608 |
|
|
// INPUTs
|
609 |
|
|
.aclk_en (aclk_en), // ACLK enable (from CPU)
|
610 |
|
|
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
|
611 |
|
|
.inclk (inclk), // INCLK external timer clock (SLOW)
|
612 |
|
|
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
|
613 |
|
|
.mclk (mclk), // Main system clock
|
614 |
|
|
.per_addr (per_addr), // Peripheral address
|
615 |
|
|
.per_din (per_din), // Peripheral data input
|
616 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
617 |
109 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
618 |
111 |
olivier.gi |
.puc_rst (puc_rst), // Main system reset
|
619 |
2 |
olivier.gi |
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
620 |
|
|
.ta_cci0a (ta_cci0a), // Timer A capture 0 input A
|
621 |
|
|
.ta_cci0b (ta_cci0b), // Timer A capture 0 input B
|
622 |
|
|
.ta_cci1a (ta_cci1a), // Timer A capture 1 input A
|
623 |
|
|
.ta_cci1b (1'b0), // Timer A capture 1 input B
|
624 |
|
|
.ta_cci2a (ta_cci2a), // Timer A capture 2 input A
|
625 |
|
|
.ta_cci2b (1'b0), // Timer A capture 2 input B
|
626 |
|
|
.taclk (taclk) // TACLK external timer clock (SLOW)
|
627 |
|
|
);
|
628 |
|
|
|
629 |
|
|
|
630 |
|
|
//
|
631 |
|
|
// Four-Digit, Seven-Segment LED Display driver
|
632 |
|
|
//----------------------------------------------
|
633 |
|
|
|
634 |
|
|
driver_7segment driver_7segment_0 (
|
635 |
|
|
|
636 |
|
|
// OUTPUTs
|
637 |
|
|
.per_dout (per_dout_7seg), // Peripheral data output
|
638 |
|
|
.seg_a (seg_a_), // Segment A control
|
639 |
|
|
.seg_b (seg_b_), // Segment B control
|
640 |
|
|
.seg_c (seg_c_), // Segment C control
|
641 |
|
|
.seg_d (seg_d_), // Segment D control
|
642 |
|
|
.seg_e (seg_e_), // Segment E control
|
643 |
|
|
.seg_f (seg_f_), // Segment F control
|
644 |
|
|
.seg_g (seg_g_), // Segment G control
|
645 |
|
|
.seg_dp (seg_dp_), // Segment DP control
|
646 |
|
|
.seg_an0 (seg_an0_), // Anode 0 control
|
647 |
|
|
.seg_an1 (seg_an1_), // Anode 1 control
|
648 |
|
|
.seg_an2 (seg_an2_), // Anode 2 control
|
649 |
|
|
.seg_an3 (seg_an3_), // Anode 3 control
|
650 |
|
|
|
651 |
|
|
// INPUTs
|
652 |
|
|
.mclk (mclk), // Main system clock
|
653 |
|
|
.per_addr (per_addr), // Peripheral address
|
654 |
|
|
.per_din (per_din), // Peripheral data input
|
655 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
656 |
109 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
657 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
658 |
2 |
olivier.gi |
);
|
659 |
|
|
|
660 |
|
|
|
661 |
|
|
//
|
662 |
136 |
olivier.gi |
// Simple full duplex UART (8N1 protocol)
|
663 |
|
|
//----------------------------------------
|
664 |
|
|
|
665 |
|
|
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (
|
666 |
|
|
|
667 |
|
|
// OUTPUTs
|
668 |
|
|
.irq_uart_rx (irq_uart_rx), // UART receive interrupt
|
669 |
|
|
.irq_uart_tx (irq_uart_tx), // UART transmit interrupt
|
670 |
|
|
.per_dout (per_dout_uart), // Peripheral data output
|
671 |
|
|
.uart_txd (hw_uart_txd), // UART Data Transmit (TXD)
|
672 |
|
|
|
673 |
|
|
// INPUTs
|
674 |
|
|
.mclk (mclk), // Main system clock
|
675 |
|
|
.per_addr (per_addr), // Peripheral address
|
676 |
|
|
.per_din (per_din), // Peripheral data input
|
677 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
678 |
|
|
.per_we (per_we), // Peripheral write enable (high active)
|
679 |
|
|
.puc_rst (puc_rst), // Main system reset
|
680 |
|
|
.smclk_en (smclk_en), // SMCLK enable (from CPU)
|
681 |
|
|
.uart_rxd (hw_uart_rxd) // UART Data Receive (RXD)
|
682 |
|
|
);
|
683 |
|
|
|
684 |
|
|
|
685 |
|
|
//
|
686 |
2 |
olivier.gi |
// Combine peripheral data buses
|
687 |
|
|
//-------------------------------
|
688 |
|
|
|
689 |
|
|
assign per_dout = per_dout_dio |
|
690 |
|
|
per_dout_tA |
|
691 |
136 |
olivier.gi |
per_dout_7seg |
|
692 |
|
|
per_dout_uart;
|
693 |
2 |
olivier.gi |
|
694 |
|
|
//
|
695 |
|
|
// Assign interrupts
|
696 |
|
|
//-------------------------------
|
697 |
|
|
|
698 |
|
|
assign nmi = 1'b0;
|
699 |
|
|
assign irq_bus = {1'b0, // Vector 13 (0xFFFA)
|
700 |
|
|
1'b0, // Vector 12 (0xFFF8)
|
701 |
|
|
1'b0, // Vector 11 (0xFFF6)
|
702 |
|
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
703 |
|
|
irq_ta0, // Vector 9 (0xFFF2)
|
704 |
|
|
irq_ta1, // Vector 8 (0xFFF0)
|
705 |
136 |
olivier.gi |
irq_uart_rx, // Vector 7 (0xFFEE)
|
706 |
|
|
irq_uart_tx, // Vector 6 (0xFFEC)
|
707 |
2 |
olivier.gi |
1'b0, // Vector 5 (0xFFEA)
|
708 |
|
|
1'b0, // Vector 4 (0xFFE8)
|
709 |
|
|
irq_port2, // Vector 3 (0xFFE6)
|
710 |
|
|
irq_port1, // Vector 2 (0xFFE4)
|
711 |
|
|
1'b0, // Vector 1 (0xFFE2)
|
712 |
|
|
1'b0}; // Vector 0 (0xFFE0)
|
713 |
|
|
|
714 |
|
|
//
|
715 |
|
|
// GPIO Function selection
|
716 |
|
|
//--------------------------
|
717 |
|
|
|
718 |
|
|
// P1.0/TACLK I/O pin / Timer_A, clock signal TACLK input
|
719 |
|
|
// P1.1/TA0 I/O pin / Timer_A, capture: CCI0A input, compare: Out0 output
|
720 |
|
|
// P1.2/TA1 I/O pin / Timer_A, capture: CCI1A input, compare: Out1 output
|
721 |
|
|
// P1.3/TA2 I/O pin / Timer_A, capture: CCI2A input, compare: Out2 output
|
722 |
|
|
// P1.4/SMCLK I/O pin / SMCLK signal output
|
723 |
|
|
// P1.5/TA0 I/O pin / Timer_A, compare: Out0 output
|
724 |
|
|
// P1.6/TA1 I/O pin / Timer_A, compare: Out1 output
|
725 |
|
|
// P1.7/TA2 I/O pin / Timer_A, compare: Out2 output
|
726 |
|
|
wire [7:0] p1_io_mux_b_unconnected;
|
727 |
|
|
wire [7:0] p1_io_dout;
|
728 |
|
|
wire [7:0] p1_io_dout_en;
|
729 |
|
|
wire [7:0] p1_io_din;
|
730 |
|
|
|
731 |
|
|
io_mux #8 io_mux_p1 (
|
732 |
|
|
.a_din (p1_din),
|
733 |
|
|
.a_dout (p1_dout),
|
734 |
|
|
.a_dout_en (p1_dout_en),
|
735 |
|
|
|
736 |
|
|
.b_din ({p1_io_mux_b_unconnected[7],
|
737 |
|
|
p1_io_mux_b_unconnected[6],
|
738 |
|
|
p1_io_mux_b_unconnected[5],
|
739 |
|
|
p1_io_mux_b_unconnected[4],
|
740 |
|
|
ta_cci2a,
|
741 |
|
|
ta_cci1a,
|
742 |
|
|
ta_cci0a,
|
743 |
|
|
taclk
|
744 |
|
|
}),
|
745 |
|
|
.b_dout ({ta_out2,
|
746 |
|
|
ta_out1,
|
747 |
|
|
ta_out0,
|
748 |
|
|
(smclk_en & mclk),
|
749 |
|
|
ta_out2,
|
750 |
|
|
ta_out1,
|
751 |
|
|
ta_out0,
|
752 |
|
|
1'b0
|
753 |
|
|
}),
|
754 |
|
|
.b_dout_en ({ta_out2_en,
|
755 |
|
|
ta_out1_en,
|
756 |
|
|
ta_out0_en,
|
757 |
|
|
1'b1,
|
758 |
|
|
ta_out2_en,
|
759 |
|
|
ta_out1_en,
|
760 |
|
|
ta_out0_en,
|
761 |
|
|
1'b0
|
762 |
|
|
}),
|
763 |
|
|
|
764 |
|
|
.io_din (p1_io_din),
|
765 |
|
|
.io_dout (p1_io_dout),
|
766 |
|
|
.io_dout_en (p1_io_dout_en),
|
767 |
|
|
|
768 |
|
|
.sel (p1_sel)
|
769 |
|
|
);
|
770 |
|
|
|
771 |
|
|
|
772 |
|
|
|
773 |
|
|
// P2.0/ACLK I/O pin / ACLK output
|
774 |
|
|
// P2.1/INCLK I/O pin / Timer_A, clock signal at INCLK
|
775 |
|
|
// P2.2/TA0 I/O pin / Timer_A, capture: CCI0B input
|
776 |
|
|
// P2.3/TA1 I/O pin / Timer_A, compare: Out1 output
|
777 |
|
|
// P2.4/TA2 I/O pin / Timer_A, compare: Out2 output
|
778 |
|
|
wire [7:0] p2_io_mux_b_unconnected;
|
779 |
|
|
wire [7:0] p2_io_dout;
|
780 |
|
|
wire [7:0] p2_io_dout_en;
|
781 |
|
|
wire [7:0] p2_io_din;
|
782 |
|
|
|
783 |
|
|
io_mux #8 io_mux_p2 (
|
784 |
|
|
.a_din (p2_din),
|
785 |
|
|
.a_dout (p2_dout),
|
786 |
|
|
.a_dout_en (p2_dout_en),
|
787 |
|
|
|
788 |
|
|
.b_din ({p2_io_mux_b_unconnected[7],
|
789 |
|
|
p2_io_mux_b_unconnected[6],
|
790 |
|
|
p2_io_mux_b_unconnected[5],
|
791 |
|
|
p2_io_mux_b_unconnected[4],
|
792 |
|
|
p2_io_mux_b_unconnected[3],
|
793 |
|
|
ta_cci0b,
|
794 |
|
|
inclk,
|
795 |
|
|
p2_io_mux_b_unconnected[0]
|
796 |
|
|
}),
|
797 |
|
|
.b_dout ({1'b0,
|
798 |
|
|
1'b0,
|
799 |
|
|
1'b0,
|
800 |
|
|
ta_out2,
|
801 |
|
|
ta_out1,
|
802 |
|
|
1'b0,
|
803 |
|
|
1'b0,
|
804 |
|
|
(aclk_en & mclk)
|
805 |
|
|
}),
|
806 |
|
|
.b_dout_en ({1'b0,
|
807 |
|
|
1'b0,
|
808 |
|
|
1'b0,
|
809 |
|
|
ta_out2_en,
|
810 |
|
|
ta_out1_en,
|
811 |
|
|
1'b0,
|
812 |
|
|
1'b0,
|
813 |
|
|
1'b1
|
814 |
|
|
}),
|
815 |
|
|
|
816 |
|
|
.io_din (p2_io_din),
|
817 |
|
|
.io_dout (p2_io_dout),
|
818 |
|
|
.io_dout_en (p2_io_dout_en),
|
819 |
|
|
|
820 |
|
|
.sel (p2_sel)
|
821 |
|
|
);
|
822 |
|
|
|
823 |
|
|
|
824 |
|
|
//=============================================================================
|
825 |
37 |
olivier.gi |
// 6) PROGRAM AND DATA MEMORIES
|
826 |
2 |
olivier.gi |
//=============================================================================
|
827 |
|
|
|
828 |
37 |
olivier.gi |
// Data Memory
|
829 |
2 |
olivier.gi |
ram_8x512_hi ram_8x512_hi_0 (
|
830 |
37 |
olivier.gi |
.addr (dmem_addr),
|
831 |
2 |
olivier.gi |
.clk (clk_sys),
|
832 |
37 |
olivier.gi |
.din (dmem_din[15:8]),
|
833 |
|
|
.dout (dmem_dout[15:8]),
|
834 |
|
|
.en (dmem_cen),
|
835 |
|
|
.we (dmem_wen[1])
|
836 |
2 |
olivier.gi |
);
|
837 |
|
|
ram_8x512_lo ram_8x512_lo_0 (
|
838 |
37 |
olivier.gi |
.addr (dmem_addr),
|
839 |
2 |
olivier.gi |
.clk (clk_sys),
|
840 |
37 |
olivier.gi |
.din (dmem_din[7:0]),
|
841 |
|
|
.dout (dmem_dout[7:0]),
|
842 |
|
|
.en (dmem_cen),
|
843 |
|
|
.we (dmem_wen[0])
|
844 |
2 |
olivier.gi |
);
|
845 |
|
|
|
846 |
|
|
|
847 |
37 |
olivier.gi |
// Program Memory
|
848 |
2 |
olivier.gi |
rom_8x2k_hi rom_8x2k_hi_0 (
|
849 |
37 |
olivier.gi |
.addr (pmem_addr),
|
850 |
2 |
olivier.gi |
.clk (clk_sys),
|
851 |
37 |
olivier.gi |
.din (pmem_din[15:8]),
|
852 |
|
|
.dout (pmem_dout[15:8]),
|
853 |
|
|
.en (pmem_cen),
|
854 |
|
|
.we (pmem_wen[1])
|
855 |
2 |
olivier.gi |
);
|
856 |
|
|
|
857 |
|
|
rom_8x2k_lo rom_8x2k_lo_0 (
|
858 |
37 |
olivier.gi |
.addr (pmem_addr),
|
859 |
2 |
olivier.gi |
.clk (clk_sys),
|
860 |
37 |
olivier.gi |
.din (pmem_din[7:0]),
|
861 |
|
|
.dout (pmem_dout[7:0]),
|
862 |
|
|
.en (pmem_cen),
|
863 |
|
|
.we (pmem_wen[0])
|
864 |
2 |
olivier.gi |
);
|
865 |
|
|
|
866 |
|
|
|
867 |
|
|
|
868 |
|
|
//=============================================================================
|
869 |
|
|
// 7) I/O CELLS
|
870 |
|
|
//=============================================================================
|
871 |
|
|
|
872 |
|
|
|
873 |
|
|
// Slide Switches (Port 1 inputs)
|
874 |
|
|
//--------------------------------
|
875 |
|
|
IBUF SW7_PIN (.O(p3_din[7]), .I(SW7));
|
876 |
|
|
IBUF SW6_PIN (.O(p3_din[6]), .I(SW6));
|
877 |
|
|
IBUF SW5_PIN (.O(p3_din[5]), .I(SW5));
|
878 |
|
|
IBUF SW4_PIN (.O(p3_din[4]), .I(SW4));
|
879 |
|
|
IBUF SW3_PIN (.O(p3_din[3]), .I(SW3));
|
880 |
|
|
IBUF SW2_PIN (.O(p3_din[2]), .I(SW2));
|
881 |
|
|
IBUF SW1_PIN (.O(p3_din[1]), .I(SW1));
|
882 |
|
|
IBUF SW0_PIN (.O(p3_din[0]), .I(SW0));
|
883 |
|
|
|
884 |
|
|
// LEDs (Port 1 outputs)
|
885 |
|
|
//-----------------------
|
886 |
|
|
OBUF LED7_PIN (.I(p3_dout[7] & p3_dout_en[7]), .O(LED7));
|
887 |
|
|
OBUF LED6_PIN (.I(p3_dout[6] & p3_dout_en[6]), .O(LED6));
|
888 |
|
|
OBUF LED5_PIN (.I(p3_dout[5] & p3_dout_en[5]), .O(LED5));
|
889 |
|
|
OBUF LED4_PIN (.I(p3_dout[4] & p3_dout_en[4]), .O(LED4));
|
890 |
|
|
OBUF LED3_PIN (.I(p3_dout[3] & p3_dout_en[3]), .O(LED3));
|
891 |
|
|
OBUF LED2_PIN (.I(p3_dout[2] & p3_dout_en[2]), .O(LED2));
|
892 |
|
|
OBUF LED1_PIN (.I(p3_dout[1] & p3_dout_en[1]), .O(LED1));
|
893 |
|
|
OBUF LED0_PIN (.I(p3_dout[0] & p3_dout_en[0]), .O(LED0));
|
894 |
|
|
|
895 |
|
|
// Push Button Switches
|
896 |
|
|
//----------------------
|
897 |
|
|
IBUF BTN2_PIN (.O(), .I(BTN2));
|
898 |
|
|
IBUF BTN1_PIN (.O(), .I(BTN1));
|
899 |
|
|
IBUF BTN0_PIN (.O(), .I(BTN0));
|
900 |
|
|
|
901 |
|
|
// Four-Sigit, Seven-Segment LED Display
|
902 |
|
|
//---------------------------------------
|
903 |
|
|
OBUF SEG_A_PIN (.I(seg_a_), .O(SEG_A));
|
904 |
|
|
OBUF SEG_B_PIN (.I(seg_b_), .O(SEG_B));
|
905 |
|
|
OBUF SEG_C_PIN (.I(seg_c_), .O(SEG_C));
|
906 |
|
|
OBUF SEG_D_PIN (.I(seg_d_), .O(SEG_D));
|
907 |
|
|
OBUF SEG_E_PIN (.I(seg_e_), .O(SEG_E));
|
908 |
|
|
OBUF SEG_F_PIN (.I(seg_f_), .O(SEG_F));
|
909 |
|
|
OBUF SEG_G_PIN (.I(seg_g_), .O(SEG_G));
|
910 |
|
|
OBUF SEG_DP_PIN (.I(seg_dp_), .O(SEG_DP));
|
911 |
|
|
OBUF SEG_AN0_PIN (.I(seg_an0_), .O(SEG_AN0));
|
912 |
|
|
OBUF SEG_AN1_PIN (.I(seg_an1_), .O(SEG_AN1));
|
913 |
|
|
OBUF SEG_AN2_PIN (.I(seg_an2_), .O(SEG_AN2));
|
914 |
|
|
OBUF SEG_AN3_PIN (.I(seg_an3_), .O(SEG_AN3));
|
915 |
|
|
|
916 |
|
|
// RS-232 Port
|
917 |
|
|
//----------------------
|
918 |
|
|
// P1.1 (TX) and P2.2 (RX)
|
919 |
|
|
assign p1_io_din = 8'h00;
|
920 |
|
|
assign p2_io_din[7:3] = 5'h00;
|
921 |
|
|
assign p2_io_din[1:0] = 2'h0;
|
922 |
|
|
|
923 |
136 |
olivier.gi |
// Mux the RS-232 port between:
|
924 |
|
|
// - GPIO port P1.1 (TX) / P2.2 (RX)
|
925 |
|
|
// - the debug interface.
|
926 |
|
|
// - the simple hardware UART
|
927 |
|
|
//
|
928 |
|
|
// The mux is controlled with the SW0/SW1 switches:
|
929 |
|
|
// 00 = debug interface
|
930 |
|
|
// 01 = GPIO
|
931 |
|
|
// 10 = simple hardware uart
|
932 |
|
|
// 11 = debug interface
|
933 |
|
|
wire sdi_select = ({p3_din[1], p3_din[0]}==2'b00) |
|
934 |
|
|
({p3_din[1], p3_din[0]}==2'b11);
|
935 |
|
|
wire gpio_select = ({p3_din[1], p3_din[0]}==2'b01);
|
936 |
|
|
wire uart_select = ({p3_din[1], p3_din[0]}==2'b10);
|
937 |
|
|
|
938 |
|
|
wire uart_txd_out = gpio_select ? p1_io_dout[1] :
|
939 |
|
|
uart_select ? hw_uart_txd : dbg_uart_txd;
|
940 |
|
|
|
941 |
2 |
olivier.gi |
wire uart_rxd_in;
|
942 |
136 |
olivier.gi |
assign p2_io_din[2] = gpio_select ? uart_rxd_in : 1'b1;
|
943 |
|
|
assign hw_uart_rxd = uart_select ? uart_rxd_in : 1'b1;
|
944 |
|
|
assign dbg_uart_rxd = sdi_select ? uart_rxd_in : 1'b1;
|
945 |
2 |
olivier.gi |
|
946 |
|
|
IBUF UART_RXD_PIN (.O(uart_rxd_in), .I(UART_RXD));
|
947 |
|
|
OBUF UART_TXD_PIN (.I(uart_txd_out), .O(UART_TXD));
|
948 |
|
|
|
949 |
|
|
IBUF UART_RXD_A_PIN (.O(), .I(UART_RXD_A));
|
950 |
|
|
OBUF UART_TXD_A_PIN (.I(1'b0), .O(UART_TXD_A));
|
951 |
|
|
|
952 |
|
|
|
953 |
|
|
// PS/2 Mouse/Keyboard Port
|
954 |
|
|
//--------------------------
|
955 |
|
|
IOBUF PS2_D_PIN (.O(), .I(1'b0), .T(1'b1), .IO(PS2_D));
|
956 |
|
|
OBUF PS2_C_PIN (.I(1'b0), .O(PS2_C));
|
957 |
|
|
|
958 |
|
|
// Fast, Asynchronous SRAM
|
959 |
|
|
//--------------------------
|
960 |
|
|
OBUF SRAM_A17_PIN (.I(1'b0), .O(SRAM_A17));
|
961 |
|
|
OBUF SRAM_A16_PIN (.I(1'b0), .O(SRAM_A16));
|
962 |
|
|
OBUF SRAM_A15_PIN (.I(1'b0), .O(SRAM_A15));
|
963 |
|
|
OBUF SRAM_A14_PIN (.I(1'b0), .O(SRAM_A14));
|
964 |
|
|
OBUF SRAM_A13_PIN (.I(1'b0), .O(SRAM_A13));
|
965 |
|
|
OBUF SRAM_A12_PIN (.I(1'b0), .O(SRAM_A12));
|
966 |
|
|
OBUF SRAM_A11_PIN (.I(1'b0), .O(SRAM_A11));
|
967 |
|
|
OBUF SRAM_A10_PIN (.I(1'b0), .O(SRAM_A10));
|
968 |
|
|
OBUF SRAM_A9_PIN (.I(1'b0), .O(SRAM_A9));
|
969 |
|
|
OBUF SRAM_A8_PIN (.I(1'b0), .O(SRAM_A8));
|
970 |
|
|
OBUF SRAM_A7_PIN (.I(1'b0), .O(SRAM_A7));
|
971 |
|
|
OBUF SRAM_A6_PIN (.I(1'b0), .O(SRAM_A6));
|
972 |
|
|
OBUF SRAM_A5_PIN (.I(1'b0), .O(SRAM_A5));
|
973 |
|
|
OBUF SRAM_A4_PIN (.I(1'b0), .O(SRAM_A4));
|
974 |
|
|
OBUF SRAM_A3_PIN (.I(1'b0), .O(SRAM_A3));
|
975 |
|
|
OBUF SRAM_A2_PIN (.I(1'b0), .O(SRAM_A2));
|
976 |
|
|
OBUF SRAM_A1_PIN (.I(1'b0), .O(SRAM_A1));
|
977 |
|
|
OBUF SRAM_A0_PIN (.I(1'b0), .O(SRAM_A0));
|
978 |
|
|
OBUF SRAM_OE_PIN (.I(1'b1), .O(SRAM_OE));
|
979 |
|
|
OBUF SRAM_WE_PIN (.I(1'b1), .O(SRAM_WE));
|
980 |
|
|
IOBUF SRAM0_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO15));
|
981 |
|
|
IOBUF SRAM0_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO14));
|
982 |
|
|
IOBUF SRAM0_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO13));
|
983 |
|
|
IOBUF SRAM0_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO12));
|
984 |
|
|
IOBUF SRAM0_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO11));
|
985 |
|
|
IOBUF SRAM0_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO10));
|
986 |
|
|
IOBUF SRAM0_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO9));
|
987 |
|
|
IOBUF SRAM0_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO8));
|
988 |
|
|
IOBUF SRAM0_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO7));
|
989 |
|
|
IOBUF SRAM0_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO6));
|
990 |
|
|
IOBUF SRAM0_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO5));
|
991 |
|
|
IOBUF SRAM0_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO4));
|
992 |
|
|
IOBUF SRAM0_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO3));
|
993 |
|
|
IOBUF SRAM0_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO2));
|
994 |
|
|
IOBUF SRAM0_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO1));
|
995 |
|
|
IOBUF SRAM0_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM0_IO0));
|
996 |
|
|
OBUF SRAM0_CE1_PIN (.I(1'b1), .O(SRAM0_CE1));
|
997 |
|
|
OBUF SRAM0_UB1_PIN (.I(1'b1), .O(SRAM0_UB1));
|
998 |
|
|
OBUF SRAM0_LB1_PIN (.I(1'b1), .O(SRAM0_LB1));
|
999 |
|
|
IOBUF SRAM1_IO15_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO15));
|
1000 |
|
|
IOBUF SRAM1_IO14_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO14));
|
1001 |
|
|
IOBUF SRAM1_IO13_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO13));
|
1002 |
|
|
IOBUF SRAM1_IO12_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO12));
|
1003 |
|
|
IOBUF SRAM1_IO11_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO11));
|
1004 |
|
|
IOBUF SRAM1_IO10_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO10));
|
1005 |
|
|
IOBUF SRAM1_IO9_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO9));
|
1006 |
|
|
IOBUF SRAM1_IO8_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO8));
|
1007 |
|
|
IOBUF SRAM1_IO7_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO7));
|
1008 |
|
|
IOBUF SRAM1_IO6_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO6));
|
1009 |
|
|
IOBUF SRAM1_IO5_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO5));
|
1010 |
|
|
IOBUF SRAM1_IO4_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO4));
|
1011 |
|
|
IOBUF SRAM1_IO3_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO3));
|
1012 |
|
|
IOBUF SRAM1_IO2_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO2));
|
1013 |
|
|
IOBUF SRAM1_IO1_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO1));
|
1014 |
|
|
IOBUF SRAM1_IO0_PIN (.O(), .I(1'b0), .T(1'b1), .IO(SRAM1_IO0));
|
1015 |
|
|
OBUF SRAM1_CE2_PIN (.I(1'b1), .O(SRAM1_CE2));
|
1016 |
|
|
OBUF SRAM1_UB2_PIN (.I(1'b1), .O(SRAM1_UB2));
|
1017 |
|
|
OBUF SRAM1_LB2_PIN (.I(1'b1), .O(SRAM1_LB2));
|
1018 |
|
|
|
1019 |
|
|
// VGA Port
|
1020 |
|
|
//---------------------------------------
|
1021 |
|
|
OBUF VGA_R_PIN (.I(1'b0), .O(VGA_R));
|
1022 |
|
|
OBUF VGA_G_PIN (.I(1'b0), .O(VGA_G));
|
1023 |
|
|
OBUF VGA_B_PIN (.I(1'b0), .O(VGA_B));
|
1024 |
|
|
OBUF VGA_HS_PIN (.I(1'b0), .O(VGA_HS));
|
1025 |
|
|
OBUF VGA_VS_PIN (.I(1'b0), .O(VGA_VS));
|
1026 |
|
|
|
1027 |
|
|
|
1028 |
|
|
endmodule // openMSP430_fpga
|
1029 |
|
|
|