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//----------------------------------------------------------------------------

// Copyright (C) 2001 Authors

//

// This source file may be used and distributed without restriction provided

// that this copyright statement is not removed from the file and that any

// derivative work contains the original copyright notice and the associated

// disclaimer.

//

// This source file is free software; you can redistribute it and/or modify

// it under the terms of the GNU Lesser General Public License as published

// by the Free Software Foundation; either version 2.1 of the License, or

// (at your option) any later version.

//

// This source is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public

// License for more details.

//

// You should have received a copy of the GNU Lesser General Public License

// along with this source; if not, write to the Free Software Foundation,

// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

//

//----------------------------------------------------------------------------

// 

// *File Name: openMSP430_fpga.v

// 

// *Module Description:

//                      openMSP430 FPGA Top-level for the Diligent

//                     Spartan-3 starter kit.

//

// *Author(s):

//              - Olivier Girard,    olgirard@gmail.com

//

//----------------------------------------------------------------------------

// $Rev: 23 $

// $LastChangedBy: olivier.girard $

// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $

//----------------------------------------------------------------------------

`include "timescale.v"

`include "openMSP430_defines.v"

module openMSP430_fpga (

// Clock Sources

    CLK_50MHz,

    CLK_SOCKET,

// Slide Switches

    SW7,

    SW6,

    SW5,

    SW4,

    SW3,

    SW2,

    SW1,

    SW0,

// Push Button Switches

    BTN3,

    BTN2,

    BTN1,

    BTN0,

// LEDs

    LED7,

    LED6,

    LED5,

    LED4,

    LED3,

    LED2,

    LED1,

    LED0,

// Four-Sigit, Seven-Segment LED Display

    SEG_A,

    SEG_B,

    SEG_C,

    SEG_D,

    SEG_E,

    SEG_F,

    SEG_G,

    SEG_DP,

    SEG_AN0,

    SEG_AN1,

    SEG_AN2,

    SEG_AN3,

// RS-232 Port

    UART_RXD,

    UART_TXD,

    UART_RXD_A,

    UART_TXD_A,

// PS/2 Mouse/Keyboard Port

    PS2_D,

    PS2_C,

// Fast, Asynchronous SRAM

    SRAM_A17,               // Address Bus Connections

    SRAM_A16,

    SRAM_A15,

    SRAM_A14,

    SRAM_A13,

    SRAM_A12,

    SRAM_A11,

    SRAM_A10,

    SRAM_A9,

    SRAM_A8,

    SRAM_A7,

    SRAM_A6,

    SRAM_A5,

    SRAM_A4,

    SRAM_A3,

    SRAM_A2,

    SRAM_A1,

    SRAM_A0,

    SRAM_OE,                // Write enable and output enable control signals

    SRAM_WE,

    SRAM0_IO15,             // SRAM Data signals, chip enables, and byte enables

    SRAM0_IO14,

    SRAM0_IO13,

    SRAM0_IO12,

    SRAM0_IO11,

    SRAM0_IO10,

    SRAM0_IO9,

    SRAM0_IO8,

    SRAM0_IO7,

    SRAM0_IO6,

    SRAM0_IO5,

    SRAM0_IO4,

    SRAM0_IO3,

    SRAM0_IO2,

    SRAM0_IO1,

    SRAM0_IO0,

    SRAM0_CE1,

    SRAM0_UB1,

    SRAM0_LB1,

    SRAM1_IO15,

    SRAM1_IO14,

    SRAM1_IO13,

    SRAM1_IO12,

    SRAM1_IO11,

    SRAM1_IO10,

    SRAM1_IO9,

    SRAM1_IO8,

    SRAM1_IO7,

    SRAM1_IO6,

    SRAM1_IO5,

    SRAM1_IO4,

    SRAM1_IO3,

    SRAM1_IO2,

    SRAM1_IO1,

    SRAM1_IO0,

    SRAM1_CE2,

    SRAM1_UB2,

    SRAM1_LB2,

// VGA Port

    VGA_R,

    VGA_G,

    VGA_B,

    VGA_HS,

    VGA_VS

);

// Clock Sources

input     CLK_50MHz;

input     CLK_SOCKET;

// Slide Switches

input     SW7;

input     SW6;

input     SW5;

input     SW4;

input     SW3;

input     SW2;

input     SW1;

input     SW0;

// Push Button Switches

input     BTN3;

input     BTN2;

input     BTN1;

input     BTN0;

// LEDs

output    LED7;

output    LED6;

output    LED5;

output    LED4;

output    LED3;

output    LED2;

output    LED1;

output    LED0;

// Four-Sigit, Seven-Segment LED Display

output    SEG_A;

output    SEG_B;

output    SEG_C;

output    SEG_D;

output    SEG_E;

output    SEG_F;

output    SEG_G;

output    SEG_DP;

output    SEG_AN0;

output    SEG_AN1;

output    SEG_AN2;

output    SEG_AN3;

// RS-232 Port

input     UART_RXD;

output    UART_TXD;

input     UART_RXD_A;

output    UART_TXD_A;

// PS/2 Mouse/Keyboard Port

inout     PS2_D;

output    PS2_C;

// Fast, Asynchronous SRAM

output    SRAM_A17;         // Address Bus Connections

output    SRAM_A16;

output    SRAM_A15;

output    SRAM_A14;

output    SRAM_A13;

output    SRAM_A12;

output    SRAM_A11;

output    SRAM_A10;

output    SRAM_A9;

output    SRAM_A8;

output    SRAM_A7;

output    SRAM_A6;

output    SRAM_A5;

output    SRAM_A4;

output    SRAM_A3;

output    SRAM_A2;

output    SRAM_A1;

output    SRAM_A0;

output    SRAM_OE;          // Write enable and output enable control signals

output    SRAM_WE;

inout     SRAM0_IO15;       // SRAM Data signals, chip enables, and byte enables

inout     SRAM0_IO14;

inout     SRAM0_IO13;

inout     SRAM0_IO12;

inout     SRAM0_IO11;

inout     SRAM0_IO10;

inout     SRAM0_IO9;

inout     SRAM0_IO8;

inout     SRAM0_IO7;

inout     SRAM0_IO6;

inout     SRAM0_IO5;

inout     SRAM0_IO4;

inout     SRAM0_IO3;

inout     SRAM0_IO2;

inout     SRAM0_IO1;

inout     SRAM0_IO0;

output    SRAM0_CE1;

output    SRAM0_UB1;

output    SRAM0_LB1;

inout     SRAM1_IO15;

inout     SRAM1_IO14;

inout     SRAM1_IO13;

inout     SRAM1_IO12;

inout     SRAM1_IO11;

inout     SRAM1_IO10;

inout     SRAM1_IO9;

inout     SRAM1_IO8;

inout     SRAM1_IO7;

inout     SRAM1_IO6;

inout     SRAM1_IO5;

inout     SRAM1_IO4;

inout     SRAM1_IO3;

inout     SRAM1_IO2;

inout     SRAM1_IO1;

inout     SRAM1_IO0;

output    SRAM1_CE2;

output    SRAM1_UB2;

output    SRAM1_LB2;

// VGA Port

output    VGA_R;

output    VGA_G;

output    VGA_B;

output    VGA_HS;

output    VGA_VS;

//=============================================================================

// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION

//=============================================================================

// openMSP430 output buses

wire        [7:0] per_addr;

wire       [15:0] per_din;

wire        [1:0] per_wen;

wire [`RAM_MSB:0] ram_addr;

wire       [15:0] ram_din;

wire        [1:0] ram_wen;

wire [`ROM_MSB:0] rom_addr;

wire       [15:0] rom_din_dbg;

wire        [1:0] rom_wen_dbg;

wire       [13:0] irq_acc;

// openMSP430 input buses

wire       [13:0] irq_bus;

wire       [15:0] per_dout;

wire       [15:0] ram_dout;

wire       [15:0] rom_dout;

// GPIO

wire        [7:0] p1_din;

wire        [7:0] p1_dout;

wire        [7:0] p1_dout_en;

wire        [7:0] p1_sel;

wire        [7:0] p2_din;

wire        [7:0] p2_dout;

wire        [7:0] p2_dout_en;

wire        [7:0] p2_sel;

wire        [7:0] p3_din;

wire        [7:0] p3_dout;

wire        [7:0] p3_dout_en;

wire        [7:0] p3_sel;

wire       [15:0] per_dout_dio;

// Timer A

wire       [15:0] per_dout_tA;

// 7 segment driver

wire       [15:0] per_dout_7seg;

// Others

wire              reset_pin;

//=============================================================================

// 2)  CLOCK GENERATION

//=============================================================================

// Input buffers

//------------------------

IBUFG ibuf_clk_main   (.O(clk_50M_in),    .I(CLK_50MHz));

IBUFG ibuf_clk_socket (.O(clk_socket_in), .I(CLK_SOCKET));

// Digital Clock Manager

//------------------------

// Generate 20MHz clock from 50MHz on-board oscillator

//`define DCM_FX_MODE

`ifdef DCM_FX_MODE

DCM dcm_adv_clk_main (

// OUTPUTs

    .CLK0         (),

    .CLK90        (),

    .CLK180       (),

    .CLK270       (),

    .CLK2X        (),

    .CLK2X180     (),

    .CLKDV        (),

    .CLKFX        (dcm_clk),

    .CLKFX180     (),

    .PSDONE       (),

    .STATUS       (),

    .LOCKED       (dcm_locked),

// INPUTs

    .CLKIN        (clk_50M_in),

    .CLKFB        (1'b0),

    .PSINCDEC     (1'b0),

    .PSEN         (1'b0),

    .DSSEN        (1'b0),

    .RST          (reset_pin),

    .PSCLK        (1'b0)

);

// synopsys translate_off

defparam dcm_adv_clk_main.CLK_FEEDBACK          = "NONE";

defparam dcm_adv_clk_main.CLKDV_DIVIDE          = 2.5;

defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2     = "FALSE";

defparam dcm_adv_clk_main.CLKIN_PERIOD          = 20.0;

defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT    = "NONE";

defparam dcm_adv_clk_main.DESKEW_ADJUST         = "SYSTEM_SYNCHRONOUS";

defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE    = "LOW";

defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE    = "LOW";

defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";

defparam dcm_adv_clk_main.FACTORY_JF            = 16'hC080;

defparam dcm_adv_clk_main.PHASE_SHIFT           = 0;

defparam dcm_adv_clk_main.STARTUP_WAIT          = "FALSE";

defparam dcm_adv_clk_main.CLKFX_DIVIDE          = 5;

defparam dcm_adv_clk_main.CLKFX_MULTIPLY        = 2;

// synopsys translate_on

`else

DCM dcm_adv_clk_main (

// OUTPUTs

    .CLKDV        (dcm_clk),

    .CLKFX        (),

    .CLKFX180     (),

    .CLK0         (CLK0_BUF),

    .CLK2X        (),

    .CLK2X180     (),

    .CLK90        (),

    .CLK180       (),

    .CLK270       (),

    .LOCKED       (dcm_locked),

    .PSDONE       (),

    .STATUS       (),

// INPUTs

    .CLKFB        (CLKFB_IN),

    .CLKIN        (clk_50M_in),

    .PSEN         (1'b0),

    .PSINCDEC     (1'b0),

    .DSSEN        (1'b0),

    .PSCLK        (1'b0),

    .RST          (reset_pin)

);

BUFG CLK0_BUFG_INST (

    .I(CLK0_BUF),

    .O(CLKFB_IN)

);

// synopsys translate_off

defparam dcm_adv_clk_main.CLK_FEEDBACK          = "1X";

defparam dcm_adv_clk_main.CLKDV_DIVIDE          = 2.5;

defparam dcm_adv_clk_main.CLKFX_DIVIDE          = 1;

defparam dcm_adv_clk_main.CLKFX_MULTIPLY        = 4;

defparam dcm_adv_clk_main.CLKIN_DIVIDE_BY_2     = "FALSE";

defparam dcm_adv_clk_main.CLKIN_PERIOD          = 20.000;

defparam dcm_adv_clk_main.CLKOUT_PHASE_SHIFT    = "NONE";

defparam dcm_adv_clk_main.DESKEW_ADJUST         = "SYSTEM_SYNCHRONOUS";

defparam dcm_adv_clk_main.DFS_FREQUENCY_MODE    = "LOW";

defparam dcm_adv_clk_main.DLL_FREQUENCY_MODE    = "LOW";

defparam dcm_adv_clk_main.DUTY_CYCLE_CORRECTION = "TRUE";

defparam dcm_adv_clk_main.FACTORY_JF            = 16'h8080;

defparam dcm_adv_clk_main.PHASE_SHIFT           = 0;

defparam dcm_adv_clk_main.STARTUP_WAIT          = "FALSE";

// synopsys translate_on  

`endif

//wire    dcm_locked = 1'b1;

//wire      reset_n;

//reg     dcm_clk;

//always @(posedge clk_50M_in)

//  if (~reset_n) dcm_clk <= 1'b0;

//  else          dcm_clk <= ~dcm_clk;

// Clock buffers

//------------------------

BUFG  buf_sys_clock  (.O(clk_sys), .I(dcm_clk));

//=============================================================================

// 3)  RESET GENERATION & FPGA STARTUP

//=============================================================================

// Reset input buffer

IBUF   ibuf_reset_n   (.O(reset_pin), .I(BTN3));

wire reset_pin_n = ~reset_pin;

// Release the reset only, if the DCM is locked

assign  reset_n = reset_pin_n & dcm_locked;

//Include the startup device   

wire  gsr_tb;

wire  gts_tb;

STARTUP_SPARTAN3 xstartup (.CLK(clk_sys), .GSR(gsr_tb), .GTS(gts_tb));

//=============================================================================

// 4)  OPENMSP430

//=============================================================================

openMSP430 openMSP430_0 (

// OUTPUTs

    .aclk_en      (aclk_en),      // ACLK enable

    .dbg_freeze   (dbg_freeze),   // Freeze peripherals

    .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD

    .irq_acc      (irq_acc),      // Interrupt request accepted (one-hot signal)

    .mclk         (mclk),         // Main system clock

    .per_addr     (per_addr),     // Peripheral address

    .per_din      (per_din),      // Peripheral data input

    .per_wen      (per_wen),      // Peripheral write enable (high active)

    .per_en       (per_en),       // Peripheral enable (high active)

    .puc          (puc),          // Main system reset

    .ram_addr     (ram_addr),     // RAM address

    .ram_cen      (ram_cen),      // RAM chip enable (low active)

    .ram_din      (ram_din),      // RAM data input

    .ram_wen      (ram_wen),      // RAM write enable (low active)

    .rom_addr     (rom_addr),     // ROM address

    .rom_cen      (rom_cen),      // ROM chip enable (low active)

    .rom_din_dbg  (rom_din_dbg),  // ROM data input --FOR DEBUG INTERFACE--

    .rom_wen_dbg  (rom_wen_dbg),  // ROM write enable (low active) --FOR DBG IF--

    .smclk_en     (smclk_en),     // SMCLK enable

// INPUTs

    .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD

    .dco_clk      (clk_sys),      // Fast oscillator (fast clock)

    .irq          (irq_bus),      // Maskable interrupts

    .lfxt_clk     (1'b0),         // Low frequency oscillator (typ 32kHz)

    .nmi          (nmi),          // Non-maskable interrupt (asynchronous)

    .per_dout     (per_dout),     // Peripheral data output

    .ram_dout     (ram_dout),     // RAM data output

    .reset_n      (reset_n),      // Reset Pin (low active)

    .rom_dout     (rom_dout)      // ROM data output

);

//=============================================================================

// 5)  OPENMSP430 PERIPHERALS

//=============================================================================

//

// Digital I/O

//-------------------------------

gpio #(.P1_EN(1),

       .P2_EN(1),

       .P3_EN(1),

       .P4_EN(0),

       .P5_EN(0),

       .P6_EN(0)) gpio_0 (

// OUTPUTs

    .irq_port1    (irq_port1),     // Port 1 interrupt

    .irq_port2    (irq_port2),     // Port 2 interrupt

    .p1_dout      (p1_dout),       // Port 1 data output

    .p1_dout_en   (p1_dout_en),    // Port 1 data output enable

    .p1_sel       (p1_sel),        // Port 1 function select

    .p2_dout      (p2_dout),       // Port 2 data output

    .p2_dout_en   (p2_dout_en),    // Port 2 data output enable

    .p2_sel       (p2_sel),        // Port 2 function select

    .p3_dout      (p3_dout),       // Port 3 data output

    .p3_dout_en   (p3_dout_en),    // Port 3 data output enable

    .p3_sel       (p3_sel),        // Port 3 function select

    .p4_dout      (),              // Port 4 data output

    .p4_dout_en   (),              // Port 4 data output enable

    .p4_sel       (),              // Port 4 function select

    .p5_dout      (),              // Port 5 data output

    .p5_dout_en   (),              // Port 5 data output enable

    .p5_sel       (),              // Port 5 function select

    .p6_dout      (),              // Port 6 data output

    .p6_dout_en   (),              // Port 6 data output enable

    .p6_sel       (),              // Port 6 function select

    .per_dout     (per_dout_dio),  // Peripheral data output

// INPUTs

    .mclk         (mclk),          // Main system clock

    .p1_din       (p1_din),        // Port 1 data input

    .p2_din       (p2_din),        // Port 2 data input

    .p3_din       (p3_din),        // Port 3 data input

    .p4_din       (8'h00),         // Port 4 data input

    .p5_din       (8'h00),         // Port 5 data input

    .p6_din       (8'h00),         // Port 6 data input

    .per_addr     (per_addr),      // Peripheral address

    .per_din      (per_din),       // Peripheral data input

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_wen      (per_wen),       // Peripheral write enable (high active)

    .puc          (puc)            // Main system reset

);

//

// Timer A

//----------------------------------------------

timerA timerA_0 (

// OUTPUTs

    .irq_ta0      (irq_ta0),       // Timer A interrupt: TACCR0

    .irq_ta1      (irq_ta1),       // Timer A interrupt: TAIV, TACCR1, TACCR2

    .per_dout     (per_dout_tA),   // Peripheral data output

    .ta_out0      (ta_out0),       // Timer A output 0

    .ta_out0_en   (ta_out0_en),    // Timer A output 0 enable

    .ta_out1      (ta_out1),       // Timer A output 1

    .ta_out1_en   (ta_out1_en),    // Timer A output 1 enable

    .ta_out2      (ta_out2),       // Timer A output 2

    .ta_out2_en   (ta_out2_en),    // Timer A output 2 enable

// INPUTs

    .aclk_en      (aclk_en),       // ACLK enable (from CPU)

    .dbg_freeze   (dbg_freeze),    // Freeze Timer A counter

    .inclk        (inclk),         // INCLK external timer clock (SLOW)

    .irq_ta0_acc  (irq_acc[9]),    // Interrupt request TACCR0 accepted

    .mclk         (mclk),          // Main system clock

    .per_addr     (per_addr),      // Peripheral address

    .per_din      (per_din),       // Peripheral data input

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_wen      (per_wen),       // Peripheral write enable (high active)

    .puc          (puc),           // Main system reset

    .smclk_en     (smclk_en),      // SMCLK enable (from CPU)

    .ta_cci0a     (ta_cci0a),      // Timer A capture 0 input A

    .ta_cci0b     (ta_cci0b),      // Timer A capture 0 input B

    .ta_cci1a     (ta_cci1a),      // Timer A capture 1 input A

    .ta_cci1b     (1'b0),          // Timer A capture 1 input B

    .ta_cci2a     (ta_cci2a),      // Timer A capture 2 input A

    .ta_cci2b     (1'b0),          // Timer A capture 2 input B

    .taclk        (taclk)          // TACLK external timer clock (SLOW)

);

//

// Four-Digit, Seven-Segment LED Display driver

//----------------------------------------------

driver_7segment driver_7segment_0 (

// OUTPUTs

    .per_dout     (per_dout_7seg), // Peripheral data output

    .seg_a        (seg_a_),        // Segment A control

    .seg_b        (seg_b_),        // Segment B control

    .seg_c        (seg_c_),        // Segment C control

    .seg_d        (seg_d_),        // Segment D control

    .seg_e        (seg_e_),        // Segment E control

    .seg_f        (seg_f_),        // Segment F control

    .seg_g        (seg_g_),        // Segment G control

    .seg_dp       (seg_dp_),       // Segment DP control

    .seg_an0      (seg_an0_),      // Anode 0 control

    .seg_an1      (seg_an1_),      // Anode 1 control

    .seg_an2      (seg_an2_),      // Anode 2 control

    .seg_an3      (seg_an3_),      // Anode 3 control

// INPUTs

    .mclk         (mclk),          // Main system clock

    .per_addr     (per_addr),      // Peripheral address

    .per_din      (per_din),       // Peripheral data input

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_wen      (per_wen),       // Peripheral write enable (high active)

    .puc          (puc)            // Main system reset

);

//

// Combine peripheral data buses

//-------------------------------

assign per_dout = per_dout_dio  |

                  per_dout_tA   |

                  per_dout_7seg;

//

// Assign interrupts

//-------------------------------

assign nmi        =  1'b0;

assign irq_bus    = {1'b0,         // Vector 13  (0xFFFA)

                     1'b0,         // Vector 12  (0xFFF8)

                     1'b0,         // Vector 11  (0xFFF6)

                     1'b0,         // Vector 10  (0xFFF4) - Watchdog -

                     irq_ta0,      // Vector  9  (0xFFF2)

                     irq_ta1,      // Vector  8  (0xFFF0)

                     1'b0,         // Vector  7  (0xFFEE)

                     1'b0,         // Vector  6  (0xFFEC)

                     1'b0,         // Vector  5  (0xFFEA)

                     1'b0,         // Vector  4  (0xFFE8)

                     irq_port2,    // Vector  3  (0xFFE6)

                     irq_port1,    // Vector  2  (0xFFE4)

                     1'b0,         // Vector  1  (0xFFE2)

                     1'b0};        // Vector  0  (0xFFE0)

//

// GPIO Function selection

//--------------------------

// P1.0/TACLK      I/O pin / Timer_A, clock signal TACLK input

// P1.1/TA0        I/O pin / Timer_A, capture: CCI0A input, compare: Out0 output

// P1.2/TA1        I/O pin / Timer_A, capture: CCI1A input, compare: Out1 output

// P1.3/TA2        I/O pin / Timer_A, capture: CCI2A input, compare: Out2 output

// P1.4/SMCLK      I/O pin / SMCLK signal output

// P1.5/TA0        I/O pin / Timer_A, compare: Out0 output

// P1.6/TA1        I/O pin / Timer_A, compare: Out1 output

// P1.7/TA2        I/O pin / Timer_A, compare: Out2 output

wire [7:0] p1_io_mux_b_unconnected;

wire [7:0] p1_io_dout;

wire [7:0] p1_io_dout_en;

wire [7:0] p1_io_din;

io_mux #8 io_mux_p1 (

                     .a_din      (p1_din),

                     .a_dout     (p1_dout),

                     .a_dout_en  (p1_dout_en),

                     .b_din      ({p1_io_mux_b_unconnected[7],

                                   p1_io_mux_b_unconnected[6],

                                   p1_io_mux_b_unconnected[5],

                                   p1_io_mux_b_unconnected[4],

                                   ta_cci2a,

                                   ta_cci1a,

                                   ta_cci0a,

                                   taclk

                                  }),

                     .b_dout     ({ta_out2,

                                   ta_out1,

                                   ta_out0,

                                   (smclk_en & mclk),

                                   ta_out2,

                                   ta_out1,

                                   ta_out0,

                                   1'b0

                                  }),

                     .b_dout_en  ({ta_out2_en,

                                   ta_out1_en,

                                   ta_out0_en,

                                   1'b1,