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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg_uart.v] - Blame information for rev 105

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Line No. Rev Author Line
1 2 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
25 34 olivier.gi
// *File Name: omsp_dbg_uart.v
26 2 olivier.gi
// 
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// *Module Description:
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//                       Debug UART communication interface (8N1, Half-duplex)
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
34 17 olivier.gi
// $Rev: 105 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-10 22:10:30 +0100 (Thu, 10 Mar 2011) $
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//----------------------------------------------------------------------------
38 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
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`else
40 23 olivier.gi
`include "openMSP430_defines.v"
41 104 olivier.gi
`endif
42 2 olivier.gi
 
43 34 olivier.gi
module  omsp_dbg_uart (
44 2 olivier.gi
 
45
// OUTPUTs
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    dbg_addr,                       // Debug register address
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    dbg_din,                        // Debug register data input
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    dbg_rd,                         // Debug register data read
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    dbg_uart_txd,                   // Debug interface: UART TXD
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    dbg_wr,                         // Debug register data write
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// INPUTs
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    dbg_dout,                       // Debug register data output
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    dbg_rd_rdy,                     // Debug register data is ready for read
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    dbg_uart_rxd,                   // Debug interface: UART RXD
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    mclk,                           // Main system clock
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    mem_burst,                      // Burst on going
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    mem_burst_end,                  // End TX/RX burst
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    mem_burst_rd,                   // Start TX burst
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    mem_burst_wr,                   // Start RX burst
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    mem_bw,                         // Burst byte width
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    por                             // Power on reset
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);
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65
// OUTPUTs
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//=========
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output        [5:0] dbg_addr;       // Debug register address
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output       [15:0] dbg_din;        // Debug register data input
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output              dbg_rd;         // Debug register data read
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output              dbg_uart_txd;   // Debug interface: UART TXD
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output              dbg_wr;         // Debug register data write
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73
// INPUTs
74
//=========
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input        [15:0] dbg_dout;       // Debug register data output
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input               dbg_rd_rdy;     // Debug register data is ready for read
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input               dbg_uart_rxd;   // Debug interface: UART RXD
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input               mclk;           // Main system clock
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input               mem_burst;      // Burst on going
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input               mem_burst_end;  // End TX/RX burst
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input               mem_burst_rd;   // Start TX burst
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input               mem_burst_wr;   // Start RX burst
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input               mem_bw;         // Burst byte width
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input               por;            // Power on reset
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86
 
87
//=============================================================================
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// 1)  UART RECEIVE LINE SYNCHRONIZTION & FILTERING
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//=============================================================================
90
 
91
// Synchronize RXD input & buffer
92
//--------------------------------
93
reg  [3:0] rxd_sync;
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always @ (posedge mclk or posedge por)
95 105 olivier.gi
  if (por) rxd_sync <=  4'hf;
96 2 olivier.gi
  else     rxd_sync <=  {rxd_sync[2:0], dbg_uart_rxd};
97
 
98
// Majority decision
99
//------------------------
100
reg        rxd_maj;
101
 
102
wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} +
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                         {1'b0, rxd_sync[2]} +
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                         {1'b0, rxd_sync[3]};
105
wire       rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
106
 
107
always @ (posedge mclk or posedge por)
108
  if (por) rxd_maj <=  1'b0;
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  else     rxd_maj <=  rxd_maj_nxt;
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111
wire rxd_s  =  rxd_maj;
112
wire rxd_fe =  rxd_maj & ~rxd_maj_nxt;
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wire rxd_re = ~rxd_maj &  rxd_maj_nxt;
114
 
115
 
116
//=============================================================================
117
// 2)  UART STATE MACHINE
118
//=============================================================================
119
 
120
// Receive state
121
//------------------------
122
reg  [2:0] uart_state;
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reg  [2:0] uart_state_nxt;
124
 
125
wire       sync_done;
126
wire       xfer_done;
127
reg [19:0] xfer_buf;
128
 
129
// State machine definition
130
parameter  RX_SYNC  = 3'h0;
131
parameter  RX_CMD   = 3'h1;
132
parameter  RX_DATA1 = 3'h2;
133
parameter  RX_DATA2 = 3'h3;
134
parameter  TX_DATA1 = 3'h4;
135
parameter  TX_DATA2 = 3'h5;
136
 
137
// State transition
138
always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
139
  case (uart_state)
140
    RX_SYNC  : uart_state_nxt =  RX_CMD;
141
    RX_CMD   : uart_state_nxt =  mem_burst_wr                ?
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                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
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                                 mem_burst_rd                ?
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                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
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                                (xfer_buf[`DBG_UART_WR]      ?
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                                (xfer_buf[`DBG_UART_BW]      ? RX_DATA2 : RX_DATA1) :
147
                                (xfer_buf[`DBG_UART_BW]      ? TX_DATA2 : TX_DATA1));
148
    RX_DATA1 : uart_state_nxt =  RX_DATA2;
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    RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
150
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
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                                 RX_CMD;
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    TX_DATA1 : uart_state_nxt =  TX_DATA2;
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    TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
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                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
155
                                 RX_CMD;
156
    default  : uart_state_nxt =  RX_CMD;
157
  endcase
158
 
159
// State machine
160
always @(posedge mclk or posedge por)
161
  if (por)                              uart_state <= RX_SYNC;
162
  else if (xfer_done    | sync_done |
163
           mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
164
 
165
// Utility signals
166
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
167
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
168
 
169
 
170
//=============================================================================
171
// 3)  UART SYNCHRONIZATION
172
//=============================================================================
173
// After POR, the host needs to fist send a synchronization character (0x80)
174
// If this feature doesn't work properly, it is possible to disable it by
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// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
176
 
177
reg        sync_busy;
178
always @ (posedge mclk or posedge por)
179
  if (por)                                 sync_busy <=  1'b0;
180
  else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <=  1'b1;
181
  else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <=  1'b0;
182
 
183
assign sync_done =  (uart_state==RX_SYNC) & rxd_re & sync_busy;
184
 
185
`ifdef DBG_UART_AUTO_SYNC
186
 
187 74 olivier.gi
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
188 2 olivier.gi
always @ (posedge mclk or posedge por)
189 74 olivier.gi
  if (por)            sync_cnt <=  {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
190
  else if (sync_busy) sync_cnt <=  sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
191 2 olivier.gi
 
192 74 olivier.gi
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
193 2 olivier.gi
`else
194 74 olivier.gi
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
195 2 olivier.gi
`endif
196
 
197
 
198
//=============================================================================
199
// 4)  UART RECEIVE / TRANSMIT
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//=============================================================================
201
 
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// Transfer counter
203
//------------------------
204 74 olivier.gi
reg                      [3:0] xfer_bit;
205
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
206 2 olivier.gi
 
207
wire       txd_start    = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
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wire       rxd_start    = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
209 74 olivier.gi
wire       xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
210 2 olivier.gi
assign     xfer_done    = (xfer_bit==4'hb);
211
 
212
always @ (posedge mclk or posedge por)
213
  if (por)                           xfer_bit <=  4'h0;
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  else if (txd_start | rxd_start)    xfer_bit <=  4'h1;
215
  else if (xfer_done)                xfer_bit <=  4'h0;
216
  else if (xfer_bit_inc)             xfer_bit <=  xfer_bit+4'h1;
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218
always @ (posedge mclk or posedge por)
219 74 olivier.gi
  if (por)                           xfer_cnt <=  {`DBG_UART_XFER_CNT_W{1'b0}};
220
  else if (rxd_start)                xfer_cnt <=  {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
221 2 olivier.gi
  else if (txd_start | xfer_bit_inc) xfer_cnt <=  bit_cnt_max;
222 74 olivier.gi
  else                               xfer_cnt <=  xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
223 2 olivier.gi
 
224
 
225
// Receive/Transmit buffer
226
//-------------------------
227
wire [19:0] xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};
228
 
229
always @ (posedge mclk or posedge por)
230 85 olivier.gi
  if (por)               xfer_buf <=  20'h00000;
231 2 olivier.gi
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
232
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;
233
 
234
 
235
// Generate TXD output
236
//------------------------
237
reg dbg_uart_txd;
238
 
239
always @ (posedge mclk or posedge por)
240
  if (por)                           dbg_uart_txd <=  1'b1;
241
  else if (xfer_bit_inc & tx_active) dbg_uart_txd <=  xfer_buf[0];
242
 
243
 
244
//=============================================================================
245
// 5) INTERFACE TO DEBUG REGISTERS
246
//=============================================================================
247
 
248
reg [5:0] dbg_addr;
249
 always @ (posedge mclk or posedge por)
250
  if (por)            dbg_addr <=  6'h00;
251
  else if (cmd_valid) dbg_addr <=  xfer_buf[`DBG_UART_ADDR];
252
 
253
reg       dbg_bw;
254
always @ (posedge mclk or posedge por)
255
  if (por)            dbg_bw   <=  1'b0;
256
  else if (cmd_valid) dbg_bw   <=  xfer_buf[`DBG_UART_BW];
257
 
258
wire        dbg_din_bw =  mem_burst  ? mem_bw : dbg_bw;
259
 
260
wire [15:0] dbg_din    =  dbg_din_bw ? {8'h00,           xfer_buf[18:11]} :
261
                                       {xfer_buf[18:11], xfer_buf[8:1]};
262
wire        dbg_wr     = (xfer_done & (uart_state==RX_DATA2));
263
wire        dbg_rd     = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
264
                                     (cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd;
265
 
266
 
267
 
268 34 olivier.gi
endmodule // omsp_dbg_uart
269 2 olivier.gi
 
270 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
271
`else
272 33 olivier.gi
`include "openMSP430_undefines.v"
273 104 olivier.gi
`endif

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