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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_mem_backbone.v] - Blame information for rev 151

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1 2 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the authors nor the names of its contributors
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//       may be used to endorse or promote products derived from this software
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//       without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_mem_backbone.v
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// 
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// *Module Description:
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//                       Memory interface backbone (decoder + arbiter)
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 151 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-07-23 00:24:11 +0200 (Mon, 23 Jul 2012) $
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_defines.v"
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`endif
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48 34 olivier.gi
module  omsp_mem_backbone (
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50
// OUTPUTs
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    dbg_mem_din,                    // Debug unit Memory data input
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    dmem_addr,                      // Data Memory address
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    dmem_cen,                       // Data Memory chip enable (low active)
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    dmem_din,                       // Data Memory data input
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    dmem_wen,                       // Data Memory write enable (low active)
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    eu_mdb_in,                      // Execution Unit Memory data bus input
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    fe_mdb_in,                      // Frontend Memory data bus input
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    fe_pmem_wait,                   // Frontend wait for Instruction fetch
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    per_addr,                       // Peripheral address
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    per_din,                        // Peripheral data input
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    per_we,                         // Peripheral write enable (high active)
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    per_en,                         // Peripheral enable (high active)
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    pmem_addr,                      // Program Memory address
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    pmem_cen,                       // Program Memory chip enable (low active)
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    pmem_din,                       // Program Memory data input (optional)
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    pmem_wen,                       // Program Memory write enable (low active) (optional)
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68
// INPUTs
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    dbg_halt_st,                    // Halt/Run status from CPU
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    dbg_mem_addr,                   // Debug address for rd/wr access
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    dbg_mem_dout,                   // Debug unit data output
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    dbg_mem_en,                     // Debug unit memory enable
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    dbg_mem_wr,                     // Debug unit memory write
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    dmem_dout,                      // Data Memory data output
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    eu_mab,                         // Execution Unit Memory address bus
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    eu_mb_en,                       // Execution Unit Memory bus enable
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    eu_mb_wr,                       // Execution Unit Memory bus write transfer
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    eu_mdb_out,                     // Execution Unit Memory data bus output
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    fe_mab,                         // Frontend Memory address bus
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    fe_mb_en,                       // Frontend Memory bus enable
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    mclk,                           // Main system clock
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    per_dout,                       // Peripheral data output
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    pmem_dout,                      // Program Memory data output
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    puc_rst,                        // Main system reset
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    scan_enable                     // Scan enable (active during scan shifting)
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);
87
 
88
// OUTPUTs
89
//=========
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output        [15:0] dbg_mem_din;   // Debug unit Memory data input
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output [`DMEM_MSB:0] dmem_addr;     // Data Memory address
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output               dmem_cen;      // Data Memory chip enable (low active)
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output        [15:0] dmem_din;      // Data Memory data input
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output         [1:0] dmem_wen;      // Data Memory write enable (low active)
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output        [15:0] eu_mdb_in;     // Execution Unit Memory data bus input
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output        [15:0] fe_mdb_in;     // Frontend Memory data bus input
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output               fe_pmem_wait;  // Frontend wait for Instruction fetch
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output        [13:0] per_addr;      // Peripheral address
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output        [15:0] per_din;       // Peripheral data input
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output         [1:0] per_we;        // Peripheral write enable (high active)
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output               per_en;        // Peripheral enable (high active)
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output [`PMEM_MSB:0] pmem_addr;     // Program Memory address
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output               pmem_cen;      // Program Memory chip enable (low active)
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output        [15:0] pmem_din;      // Program Memory data input (optional)
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output         [1:0] pmem_wen;      // Program Memory write enable (low active) (optional)
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107
// INPUTs
108
//=========
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input                dbg_halt_st;   // Halt/Run status from CPU
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input         [15:0] dbg_mem_addr;  // Debug address for rd/wr access
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input         [15:0] dbg_mem_dout;  // Debug unit data output
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input                dbg_mem_en;    // Debug unit memory enable
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input          [1:0] dbg_mem_wr;    // Debug unit memory write
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input         [15:0] dmem_dout;     // Data Memory data output
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input         [14:0] eu_mab;        // Execution Unit Memory address bus
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input                eu_mb_en;      // Execution Unit Memory bus enable
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input          [1:0] eu_mb_wr;      // Execution Unit Memory bus write transfer
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input         [15:0] eu_mdb_out;    // Execution Unit Memory data bus output
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input         [14:0] fe_mab;        // Frontend Memory address bus
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input                fe_mb_en;      // Frontend Memory bus enable
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input                mclk;          // Main system clock
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input         [15:0] per_dout;      // Peripheral data output
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input         [15:0] pmem_dout;     // Program Memory data output
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input                puc_rst;       // Main system reset
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input                scan_enable;   // Scan enable (active during scan shifting)
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127
 
128
//=============================================================================
129
// 1)  DECODER
130
//=============================================================================
131
 
132
// RAM Interface
133
//------------------
134
 
135
// Execution unit access
136 33 olivier.gi
wire               eu_dmem_cen   = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
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                                                (eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
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wire        [15:0] eu_dmem_addr  = {1'b0, eu_mab}-(`DMEM_BASE>>1);
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140
// Debug interface access
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wire               dbg_dmem_cen  = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
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                                                  (dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
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wire        [15:0] dbg_dmem_addr = {1'b0, dbg_mem_addr[15:1]}-(`DMEM_BASE>>1);
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145
 
146
// RAM Interface
147 33 olivier.gi
wire [`DMEM_MSB:0] dmem_addr     = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
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wire               dmem_cen      =  dbg_dmem_cen & eu_dmem_cen;
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wire         [1:0] dmem_wen      = ~(dbg_mem_wr | eu_mb_wr);
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wire        [15:0] dmem_din      = ~dbg_dmem_cen ? dbg_mem_dout : eu_mdb_out;
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152
 
153
// ROM Interface
154
//------------------
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parameter          PMEM_OFFSET   = (16'hFFFF-`PMEM_SIZE+1);
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157
// Execution unit access (only read access are accepted)
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wire               eu_pmem_cen   = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(PMEM_OFFSET>>1)));
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wire        [15:0] eu_pmem_addr  = eu_mab-(PMEM_OFFSET>>1);
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161
// Front-end access
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wire               fe_pmem_cen   = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
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wire        [15:0] fe_pmem_addr  = fe_mab-(PMEM_OFFSET>>1);
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165
// Debug interface access
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wire               dbg_pmem_cen  = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
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wire        [15:0] dbg_pmem_addr = {1'b0, dbg_mem_addr[15:1]}-(PMEM_OFFSET>>1);
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169
 
170
// ROM Interface (Execution unit has priority)
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wire [`PMEM_MSB:0] pmem_addr     = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
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                                   ~eu_pmem_cen  ? eu_pmem_addr[`PMEM_MSB:0]  : fe_pmem_addr[`PMEM_MSB:0];
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wire               pmem_cen      =  fe_pmem_cen & eu_pmem_cen & dbg_pmem_cen;
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wire         [1:0] pmem_wen      = ~dbg_mem_wr;
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wire        [15:0] pmem_din      =  dbg_mem_dout;
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wire               fe_pmem_wait  = (~fe_pmem_cen & ~eu_pmem_cen);
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179
 
180
// Peripherals
181
//--------------------
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wire              dbg_per_en   =  dbg_mem_en & (dbg_mem_addr[15:1]<(`PER_SIZE>>1));
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wire              eu_per_en    =  eu_mb_en   & (eu_mab<(`PER_SIZE>>1));
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185 111 olivier.gi
wire       [15:0] per_din      =  dbg_mem_en ? dbg_mem_dout               : eu_mdb_out;
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wire        [1:0] per_we       =  dbg_mem_en ? dbg_mem_wr                 : eu_mb_wr;
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wire              per_en       =  dbg_mem_en ? dbg_per_en                 : eu_per_en;
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wire [`PER_MSB:0] per_addr_mux =  dbg_mem_en ? dbg_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
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wire       [14:0] per_addr_ful =  {{15-`PER_AWIDTH{1'b0}}, per_addr_mux};
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wire       [13:0] per_addr     =   per_addr_ful[13:0];
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192
reg   [15:0] per_dout_val;
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always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)  per_dout_val <= 16'h0000;
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  else          per_dout_val <= per_dout;
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197
 
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// Frontend data Mux
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//---------------------------------
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// Whenever the frontend doesn't access the ROM,  backup the data
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// Detect whenever the data should be backuped and restored
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reg         fe_pmem_cen_dly;
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always @(posedge mclk or posedge puc_rst)
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  if (puc_rst) fe_pmem_cen_dly <=  1'b0;
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  else         fe_pmem_cen_dly <=  fe_pmem_cen;
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208 33 olivier.gi
wire fe_pmem_save    = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
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wire fe_pmem_restore = (~fe_pmem_cen &  fe_pmem_cen_dly) |  dbg_halt_st;
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211
`ifdef CLOCK_GATING
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wire mclk_bckup;
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omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup),
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                                  .clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
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`else
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wire mclk_bckup = mclk;
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`endif
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219 33 olivier.gi
reg  [15:0] pmem_dout_bckup;
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always @(posedge mclk_bckup or posedge puc_rst)
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  if (puc_rst)           pmem_dout_bckup     <=  16'h0000;
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`ifdef CLOCK_GATING
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  else                   pmem_dout_bckup     <=  pmem_dout;
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`else
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  else if (fe_pmem_save) pmem_dout_bckup     <=  pmem_dout;
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`endif
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228
// Mux between the ROM data and the backup
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reg         pmem_dout_bckup_sel;
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always @(posedge mclk or posedge puc_rst)
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  if (puc_rst)              pmem_dout_bckup_sel <=  1'b0;
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  else if (fe_pmem_save)    pmem_dout_bckup_sel <=  1'b1;
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  else if (fe_pmem_restore) pmem_dout_bckup_sel <=  1'b0;
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assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
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// Execution-Unit data Mux
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//---------------------------------
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// Select between peripherals, RAM and ROM
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reg [1:0] eu_mdb_in_sel;
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always @(posedge mclk or posedge puc_rst)
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  if (puc_rst)  eu_mdb_in_sel <= 2'b00;
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  else          eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
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// Mux
248 33 olivier.gi
assign      eu_mdb_in      = eu_mdb_in_sel[1] ? pmem_dout    :
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                             eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
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251
// Debug interface  data Mux
252
//---------------------------------
253
 
254
// Select between peripherals, RAM and ROM
255 109 olivier.gi
`ifdef DBG_EN
256
reg   [1:0] dbg_mem_din_sel;
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always @(posedge mclk or posedge puc_rst)
258
  if (puc_rst)  dbg_mem_din_sel <= 2'b00;
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  else          dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
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261 109 olivier.gi
`else
262
wire  [1:0] dbg_mem_din_sel  = 2'b00;
263
`endif
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265 2 olivier.gi
// Mux
266 33 olivier.gi
assign      dbg_mem_din  = dbg_mem_din_sel[1] ? pmem_dout    :
267
                           dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
268 2 olivier.gi
 
269
 
270 34 olivier.gi
endmodule // omsp_mem_backbone
271 2 olivier.gi
 
272 104 olivier.gi
`ifdef OMSP_NO_INCLUDE
273
`else
274 33 olivier.gi
`include "openMSP430_undefines.v"
275 104 olivier.gi
`endif

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