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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_sfr.v] - Blame information for rev 37

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1 2 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_sfr.v
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// 
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// *Module Description:
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//                       Processor Special function register
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 37 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
38 23 olivier.gi
`include "timescale.v"
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`include "openMSP430_defines.v"
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41 34 olivier.gi
module  omsp_sfr (
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// OUTPUTs
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    nmie,                         // Non-maskable interrupt enable
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    per_dout,                     // Peripheral data output
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    wdt_irq,                      // Watchdog-timer interrupt
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    wdt_reset,                    // Watchdog-timer reset
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    wdtie,                        // Watchdog-timer interrupt enable
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// INPUTs
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    mclk,                         // Main system clock
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    nmi_acc,                      // Non-Maskable interrupt request accepted
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    per_addr,                     // Peripheral address
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    per_din,                      // Peripheral data input
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    per_en,                       // Peripheral enable (high active)
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    per_wen,                      // Peripheral write enable (high active)
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    por,                          // Power-on reset
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    puc,                          // Main system reset
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    wdtifg_clr,                   // Clear Watchdog-timer interrupt flag
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    wdtifg_set,                   // Set Watchdog-timer interrupt flag
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    wdtpw_error,                  // Watchdog-timer password error
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    wdttmsel                      // Watchdog-timer mode select
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);
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// OUTPUTs
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//=========
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output              nmie;         // Non-maskable interrupt enable
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output       [15:0] per_dout;     // Peripheral data output
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output              wdt_irq;      // Watchdog-timer interrupt
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output              wdt_reset;    // Watchdog-timer reset
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output              wdtie;        // Watchdog-timer interrupt enable
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// INPUTs
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//=========
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input               mclk;         // Main system clock
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input               nmi_acc;      // Non-Maskable interrupt request accepted
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input         [7:0] per_addr;     // Peripheral address
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input        [15:0] per_din;      // Peripheral data input
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input               per_en;       // Peripheral enable (high active)
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input         [1:0] per_wen;      // Peripheral write enable (high active)
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input               por;          // Power-on reset
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input               puc;          // Main system reset
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input               wdtifg_clr;   // Clear Watchdog-timer interrupt flag
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input               wdtifg_set;   // Set Watchdog-timer interrupt flag
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input               wdtpw_error;  // Watchdog-timer password error
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input               wdttmsel;     // Watchdog-timer mode select
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//=============================================================================
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// 1)  PARAMETER DECLARATION
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//=============================================================================
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// Register addresses
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parameter           IE1        = 9'h000;
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parameter           IFG1       = 9'h002;
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// Register one-hot decoder
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parameter           IE1_D      = (256'h1 << (IE1  /2));
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parameter           IFG1_D     = (256'h1 << (IFG1 /2));
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//============================================================================
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// 2)  REGISTER DECODER
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//============================================================================
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// Register address decode
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reg  [255:0]  reg_dec;
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always @(per_addr)
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  case (per_addr)
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    (IE1  /2):     reg_dec  =  IE1_D;
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    (IFG1 /2):     reg_dec  =  IFG1_D;
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    default  :     reg_dec  =  {256{1'b0}};
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  endcase
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// Read/Write probes
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wire         reg_lo_write =  per_wen[0] & per_en;
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wire         reg_hi_write =  per_wen[1] & per_en;
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wire         reg_read     = ~|per_wen   & per_en;
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// Read/Write vectors
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wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
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wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
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wire [255:0] reg_rd       = reg_dec & {256{reg_read}};
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//============================================================================
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// 3) REGISTERS
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//============================================================================
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// IE1 Register
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//--------------
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wire [7:0] ie1;
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wire       ie1_wr  = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2];
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wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8]    : per_din[7:0];
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reg        nmie;
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always @ (posedge mclk or posedge puc)
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  if (puc)          nmie  <=  1'b0;
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  else if (nmi_acc) nmie  <=  1'b0;
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  else if (ie1_wr)  nmie  <=  ie1_nxt[4];
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reg        wdtie;
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always @ (posedge mclk or posedge puc)
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  if (puc)           wdtie <=  1'b0;
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  else if (ie1_wr)   wdtie <=  ie1_nxt[0];
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assign  ie1 = {3'b000, nmie, 3'b000, wdtie};
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// IFG1 Register
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//---------------
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wire [7:0] ifg1;
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wire       ifg1_wr  = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2];
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wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8]     : per_din[7:0];
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reg        nmiifg;
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always @ (posedge mclk or posedge puc)
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  if (puc)           nmiifg <=  1'b0;
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  else if (nmi_acc)  nmiifg <=  1'b1;
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  else if (ifg1_wr)  nmiifg <=  ifg1_nxt[4];
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reg        wdtifg;
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always @ (posedge mclk or posedge por)
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  if (por)                        wdtifg <=  1'b0;
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  else if (wdtifg_set)            wdtifg <=  1'b1;
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  else if (wdttmsel & wdtifg_clr) wdtifg <=  1'b0;
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  else if (ifg1_wr)               wdtifg <=  ifg1_nxt[0];
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assign  ifg1 = {3'b000, nmiifg, 3'b000, wdtifg};
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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// Data output mux
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wire [15:0] ie1_rd   = (ie1  & {8{reg_rd[IE1/2]}})  << (8 & {4{IE1[0]}});
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wire [15:0] ifg1_rd  = (ifg1 & {8{reg_rd[IFG1/2]}}) << (8 & {4{IFG1[0]}});
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wire [15:0] per_dout =  ie1_rd   |
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                        ifg1_rd;
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//=============================================================================
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// 5)  WATCHDOG INTERRUPT & RESET
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//=============================================================================
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// Watchdog interrupt generation
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//---------------------------------
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wire    wdt_irq      = wdttmsel & wdtifg & wdtie;
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// Watchdog reset generation
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//-----------------------------
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reg     wdt_reset;
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always @ (posedge mclk or posedge por)
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  if (por) wdt_reset <= 1'b0;
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  else     wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
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202 34 olivier.gi
endmodule // omsp_sfr
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`include "openMSP430_undefines.v"

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