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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Blame information for rev 205

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1 2 olivier.gi
//----------------------------------------------------------------------------
2 136 olivier.gi
// Copyright (C) 2009 , Olivier Girard
3 2 olivier.gi
//
4 136 olivier.gi
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15 2 olivier.gi
//
16 136 olivier.gi
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27 2 olivier.gi
//
28
//----------------------------------------------------------------------------
29 202 olivier.gi
//
30 23 olivier.gi
// *File Name: openMSP430_defines.v
31 202 olivier.gi
//
32 2 olivier.gi
// *Module Description:
33
//                      openMSP430 Configuration file
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39 17 olivier.gi
// $Rev: 205 $
40
// $LastChangedBy: olivier.girard $
41
// $LastChangedDate: 2015-07-15 22:59:52 +0200 (Wed, 15 Jul 2015) $
42
//----------------------------------------------------------------------------
43 104 olivier.gi
//`define OMSP_NO_INCLUDE
44
`ifdef OMSP_NO_INCLUDE
45
`else
46 33 olivier.gi
`include "openMSP430_undefines.v"
47 104 olivier.gi
`endif
48 2 olivier.gi
 
49 111 olivier.gi
//============================================================================
50
//============================================================================
51
// BASIC SYSTEM CONFIGURATION
52
//============================================================================
53
//============================================================================
54 72 olivier.gi
//
55 111 olivier.gi
// Note: the sum of program, data and peripheral memory spaces must not
56
//      exceed 64 kB
57 72 olivier.gi
//
58 2 olivier.gi
 
59 33 olivier.gi
// Program Memory Size:
60 72 olivier.gi
//                     Uncomment the required memory size
61
//-------------------------------------------------------
62 151 olivier.gi
//`define PMEM_SIZE_CUSTOM
63 72 olivier.gi
//`define PMEM_SIZE_59_KB
64
//`define PMEM_SIZE_55_KB
65
//`define PMEM_SIZE_54_KB
66
//`define PMEM_SIZE_51_KB
67
//`define PMEM_SIZE_48_KB
68
//`define PMEM_SIZE_41_KB
69
//`define PMEM_SIZE_32_KB
70
//`define PMEM_SIZE_24_KB
71
//`define PMEM_SIZE_16_KB
72
//`define PMEM_SIZE_12_KB
73
//`define PMEM_SIZE_8_KB
74
`define PMEM_SIZE_4_KB
75
//`define PMEM_SIZE_2_KB
76
//`define PMEM_SIZE_1_KB
77 2 olivier.gi
 
78 111 olivier.gi
 
79 33 olivier.gi
// Data Memory Size:
80 72 olivier.gi
//                     Uncomment the required memory size
81
//-------------------------------------------------------
82 151 olivier.gi
//`define DMEM_SIZE_CUSTOM
83 72 olivier.gi
//`define DMEM_SIZE_32_KB
84
//`define DMEM_SIZE_24_KB
85
//`define DMEM_SIZE_16_KB
86
//`define DMEM_SIZE_10_KB
87
//`define DMEM_SIZE_8_KB
88
//`define DMEM_SIZE_5_KB
89
//`define DMEM_SIZE_4_KB
90
//`define DMEM_SIZE_2p5_KB
91
//`define DMEM_SIZE_2_KB
92
`define DMEM_SIZE_1_KB
93
//`define DMEM_SIZE_512_B
94
//`define DMEM_SIZE_256_B
95
//`define DMEM_SIZE_128_B
96 2 olivier.gi
 
97 111 olivier.gi
 
98 71 olivier.gi
// Include/Exclude Hardware Multiplier
99
`define MULTIPLIER
100
 
101
 
102 111 olivier.gi
// Include/Exclude Serial Debug interface
103 2 olivier.gi
`define DBG_EN
104
 
105 111 olivier.gi
 
106
//============================================================================
107
//============================================================================
108
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
109
//============================================================================
110
//============================================================================
111
 
112
//-------------------------------------------------------
113 136 olivier.gi
// Custom user version number
114
//-------------------------------------------------------
115
// This 5 bit field can be freely used in order to allow
116
// custom identification of the system through the debug
117
// interface.
118
// (see CPU_ID.USER_VERSION field in the documentation)
119
//-------------------------------------------------------
120
`define USER_VERSION 5'b00001
121
 
122
 
123
//-------------------------------------------------------
124
// Include/Exclude Watchdog timer
125
//-------------------------------------------------------
126
// When excluded, the following functionality will be
127
// lost:
128
//        - Watchog (both interval and watchdog modes)
129
//        - NMI interrupt edge selection
130
//        - Possibility to generate a software PUC reset
131
//-------------------------------------------------------
132
`define WATCHDOG
133
 
134
 
135 181 olivier.gi
//-------------------------------------------------------
136 202 olivier.gi
// Include/Exclude DMA interface support
137
//-------------------------------------------------------
138
//`define DMA_IF_EN
139
 
140
 
141
//-------------------------------------------------------
142 136 olivier.gi
// Include/Exclude Non-Maskable-Interrupt support
143
//-------------------------------------------------------
144
`define NMI
145
 
146
 
147
//-------------------------------------------------------
148 193 olivier.gi
// Number of available IRQs
149
//-------------------------------------------------------
150
// Indicates the number of interrupt vectors supported
151
// (16, 32 or 64).
152
//-------------------------------------------------------
153
`define IRQ_16
154
//`define IRQ_32
155
//`define IRQ_64
156
 
157
 
158
//-------------------------------------------------------
159 136 olivier.gi
// Input synchronizers
160
//-------------------------------------------------------
161
// In some cases, the asynchronous input ports might
162
// already be synchronized externally.
163
// If an extensive CDC design review showed that this
164
// is really the case,  the individual synchronizers
165
// can be disabled with the following defines.
166
//
167
// Notes:
168
//        - all three signals are all sampled in the MCLK domain
169
//
170
//        - the dbg_en signal reset the debug interface
171
//         when 0. Therefore make sure it is glitch free.
172
//
173
//-------------------------------------------------------
174
`define SYNC_NMI
175
`define SYNC_CPU_EN
176
`define SYNC_DBG_EN
177
 
178
 
179
//-------------------------------------------------------
180 111 olivier.gi
// Peripheral Memory Space:
181
//-------------------------------------------------------
182
// The original MSP430 architecture map the peripherals
183
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
184
// The following defines allow you to expand this space
185
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
186
// As a consequence, the data memory mapping will be
187
// shifted up and a custom linker script will therefore
188
// be required by the GCC compiler.
189
//-------------------------------------------------------
190 151 olivier.gi
//`define PER_SIZE_CUSTOM
191 111 olivier.gi
//`define PER_SIZE_32_KB
192
//`define PER_SIZE_16_KB
193
//`define PER_SIZE_8_KB
194
//`define PER_SIZE_4_KB
195
//`define PER_SIZE_2_KB
196
//`define PER_SIZE_1_KB
197
`define PER_SIZE_512_B
198
 
199
 
200
//-------------------------------------------------------
201
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
202
// (CPU break on PUC reset)
203
//-------------------------------------------------------
204
// When defined, the CPU will automatically break after
205 136 olivier.gi
// a PUC occurrence by default. This is typically useful
206 111 olivier.gi
// when the program memory can only be initialized through
207
// the serial debug interface.
208
//-------------------------------------------------------
209
//`define DBG_RST_BRK_EN
210
 
211
 
212
//============================================================================
213
//============================================================================
214
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
215
//============================================================================
216
//============================================================================
217 2 olivier.gi
//
218 111 olivier.gi
// IMPORTANT NOTE:  Please update following configuration options ONLY if
219
//                 you have a good reason to do so... and if you know what
220
//                 you are doing :-P
221
//
222
//============================================================================
223 2 olivier.gi
 
224 111 olivier.gi
//-------------------------------------------------------
225 155 olivier.gi
// Select serial debug interface protocol
226
//-------------------------------------------------------
227
//    DBG_UART -> Enable UART (8N1) debug interface
228
//    DBG_I2C  -> Enable I2C debug interface
229
//-------------------------------------------------------
230
`define DBG_UART
231
//`define DBG_I2C
232
 
233
 
234
//-------------------------------------------------------
235
// Enable the I2C broadcast address
236
//-------------------------------------------------------
237
// For multicore systems, a common I2C broadcast address
238
// can be given to all oMSP cores in order to
239
// synchronously RESET, START, STOP, or STEP all CPUs
240
// at once with a single I2C command.
241
// If you have a single openMSP430 in your system,
242
// this option can stay commented-out.
243
//-------------------------------------------------------
244
//`define DBG_I2C_BROADCAST
245
 
246
 
247
//-------------------------------------------------------
248 136 olivier.gi
// Number of hardware breakpoint/watchpoint units
249
// (each unit contains two hardware addresses available
250
// for breakpoints or watchpoints):
251 111 olivier.gi
//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
252
//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
253
//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
254
//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
255
//-------------------------------------------------------
256
// Please keep in mind that hardware breakpoints only
257
// make sense whenever the program memory is not an SRAM
258
// (i.e. Flash/OTP/ROM/...) or when you are interested
259 136 olivier.gi
// in data breakpoints.
260 111 olivier.gi
//-------------------------------------------------------
261 2 olivier.gi
`define  DBG_HWBRK_0
262 37 olivier.gi
//`define  DBG_HWBRK_1
263
//`define  DBG_HWBRK_2
264
//`define  DBG_HWBRK_3
265 2 olivier.gi
 
266
 
267 111 olivier.gi
//-------------------------------------------------------
268
// Enable/Disable the hardware breakpoint RANGE mode
269
//-------------------------------------------------------
270
// When enabled this feature allows the hardware breakpoint
271
// units to stop the cpu whenever an instruction or data
272
// access lays within an address range.
273
// Note that this feature is not supported by GDB.
274
//-------------------------------------------------------
275
//`define DBG_HWBRK_RANGE
276
 
277
 
278
//-------------------------------------------------------
279 151 olivier.gi
// Custom Program/Data and Peripheral Memory Spaces
280
//-------------------------------------------------------
281
// The following values are valid only if the
282
// corresponding *_SIZE_CUSTOM defines are uncommented:
283
//
284
//  - *_SIZE   : size of the section in bytes.
285
//  - *_AWIDTH : address port width, this value must allow
286
//               to address all WORDS of the section
287
//               (i.e. the *_SIZE divided by 2)
288
//-------------------------------------------------------
289
 
290 202 olivier.gi
// Custom Program memory    (enabled with PMEM_SIZE_CUSTOM)
291 151 olivier.gi
`define PMEM_CUSTOM_AWIDTH      10
292
`define PMEM_CUSTOM_SIZE      2048
293
 
294 202 olivier.gi
// Custom Data memory       (enabled with DMEM_SIZE_CUSTOM)
295 151 olivier.gi
`define DMEM_CUSTOM_AWIDTH       6
296
`define DMEM_CUSTOM_SIZE       128
297
 
298 202 olivier.gi
// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
299 151 olivier.gi
`define PER_CUSTOM_AWIDTH        8
300
`define PER_CUSTOM_SIZE        512
301
 
302
 
303
//-------------------------------------------------------
304 136 olivier.gi
// ASIC version
305 111 olivier.gi
//-------------------------------------------------------
306 136 olivier.gi
// When uncommented, this define will enable the
307
// ASIC system configuration section (see below) and
308
// will activate scan support for production test.
309 109 olivier.gi
//
310 136 olivier.gi
// WARNING: if you target an FPGA, leave this define
311
//          commented.
312 111 olivier.gi
//-------------------------------------------------------
313 136 olivier.gi
//`define ASIC
314 109 olivier.gi
 
315
 
316 136 olivier.gi
//============================================================================
317
//============================================================================
318
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
319
//============================================================================
320
//============================================================================
321
`ifdef ASIC
322 111 olivier.gi
 
323 136 olivier.gi
//===============================================================
324
// FINE GRAINED CLOCK GATING
325
//===============================================================
326
 
327
//-------------------------------------------------------
328
// When uncommented, this define will enable the fine
329
// grained clock gating of all registers in the core.
330
//-------------------------------------------------------
331
`define CLOCK_GATING
332
 
333
 
334
//===============================================================
335 181 olivier.gi
// ASIC CLOCKING
336
//===============================================================
337
 
338
//-------------------------------------------------------
339
// When uncommented, this define will enable the ASIC
340
// architectural clock gating as well as the advanced low
341
// power modes support (most common).
342
// Comment this out in order to get FPGA-like clocking.
343
//-------------------------------------------------------
344
`define ASIC_CLOCKING
345
 
346
 
347
`ifdef ASIC_CLOCKING
348
//===============================================================
349 136 olivier.gi
// LFXT CLOCK DOMAIN
350
//===============================================================
351
 
352
//-------------------------------------------------------
353
// When uncommented, this define will enable the lfxt_clk
354
// clock domain.
355
// When commented out, the whole chip is clocked with dco_clk.
356
//-------------------------------------------------------
357
`define LFXT_DOMAIN
358
 
359
 
360
//===============================================================
361
// CLOCK MUXES
362
//===============================================================
363
 
364
//-------------------------------------------------------
365
// MCLK: Clock Mux
366
//-------------------------------------------------------
367
// When uncommented, this define will enable the
368
// MCLK clock MUX allowing the selection between
369
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
370
// When commented, DCO_CLK is selected.
371
//-------------------------------------------------------
372
`define MCLK_MUX
373
 
374
//-------------------------------------------------------
375
// SMCLK: Clock Mux
376
//-------------------------------------------------------
377
// When uncommented, this define will enable the
378
// SMCLK clock MUX allowing the selection between
379
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
380
// When commented, DCO_CLK is selected.
381
//-------------------------------------------------------
382
`define SMCLK_MUX
383
 
384
//-------------------------------------------------------
385
// WATCHDOG: Clock Mux
386
//-------------------------------------------------------
387
// When uncommented, this define will enable the
388
// Watchdog clock MUX allowing the selection between
389
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
390
// When commented out, ACLK is selected if the
391
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
392
// selected otherwise.
393
//-------------------------------------------------------
394
`define WATCHDOG_MUX
395
//`define WATCHDOG_NOMUX_ACLK
396
 
397
 
398
//===============================================================
399
// CLOCK DIVIDERS
400
//===============================================================
401
 
402
//-------------------------------------------------------
403
// MCLK: Clock divider
404
//-------------------------------------------------------
405
// When uncommented, this define will enable the
406
// MCLK clock divider (/1/2/4/8)
407
//-------------------------------------------------------
408
`define MCLK_DIVIDER
409
 
410
//-------------------------------------------------------
411
// SMCLK: Clock divider (/1/2/4/8)
412
//-------------------------------------------------------
413
// When uncommented, this define will enable the
414
// SMCLK clock divider
415
//-------------------------------------------------------
416
`define SMCLK_DIVIDER
417
 
418
//-------------------------------------------------------
419
// ACLK: Clock divider (/1/2/4/8)
420
//-------------------------------------------------------
421
// When uncommented, this define will enable the
422
// ACLK clock divider
423
//-------------------------------------------------------
424
`define ACLK_DIVIDER
425
 
426
 
427
//===============================================================
428
// LOW POWER MODES
429
//===============================================================
430
 
431
//-------------------------------------------------------
432
// LOW POWER MODE: CPUOFF
433
//-------------------------------------------------------
434
// When uncommented, this define will include the
435
// clock gate allowing to switch off MCLK in
436
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
437
//-------------------------------------------------------
438
`define CPUOFF_EN
439
 
440
//-------------------------------------------------------
441
// LOW POWER MODE: SCG0
442
//-------------------------------------------------------
443
// When uncommented, this define will enable the
444
// DCO_ENABLE/WKUP port control (always 1 when commented).
445
// This allows to switch off the DCO oscillator in the
446
// following low power modes: LPM1, LPM3, LPM4
447
//-------------------------------------------------------
448
`define SCG0_EN
449
 
450
//-------------------------------------------------------
451
// LOW POWER MODE: SCG1
452
//-------------------------------------------------------
453
// When uncommented, this define will include the
454
// clock gate allowing to switch off SMCLK in
455
// the following low power modes: LPM2, LPM3, LPM4
456
//-------------------------------------------------------
457
`define SCG1_EN
458
 
459
//-------------------------------------------------------
460
// LOW POWER MODE: OSCOFF
461
//-------------------------------------------------------
462
// When uncommented, this define will include the
463
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
464
// port control (always 1 when commented).
465
// This allows to switch off the low frequency oscillator
466
// in the following low power modes: LPM4
467
//-------------------------------------------------------
468
`define OSCOFF_EN
469
 
470 205 olivier.gi
//-------------------------------------------------------
471
// SCAN REPAIR NEG-EDGE CLOCKED FLIP-FLOPS
472
//-------------------------------------------------------
473
// When uncommented, a scan mux will be infered to
474
// replace all inverted clocks with regular ones when
475
// in scan mode.
476
//
477
// Note: standard scan insertion tool can usually deal
478
//       with mixed rising/falling edge FF... so there
479
//       is usually no need to uncomment this.
480
//-------------------------------------------------------
481
//`define SCAN_REPAIR_INV_CLOCKS
482 136 olivier.gi
 
483
`endif
484 181 olivier.gi
`endif
485 136 olivier.gi
 
486 2 olivier.gi
//==========================================================================//
487
//==========================================================================//
488
//==========================================================================//
489
//==========================================================================//
490
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
491
//==========================================================================//
492
//==========================================================================//
493
//==========================================================================//
494
//==========================================================================//
495
 
496 72 olivier.gi
//
497 111 olivier.gi
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
498
//==================================================
499 2 olivier.gi
 
500 72 olivier.gi
// Program Memory Size
501
`ifdef PMEM_SIZE_59_KB
502
  `define PMEM_AWIDTH      15
503
  `define PMEM_SIZE     60416
504
`endif
505
`ifdef PMEM_SIZE_55_KB
506
  `define PMEM_AWIDTH      15
507
  `define PMEM_SIZE     56320
508
`endif
509
`ifdef PMEM_SIZE_54_KB
510
  `define PMEM_AWIDTH      15
511
  `define PMEM_SIZE     55296
512
`endif
513
`ifdef PMEM_SIZE_51_KB
514
  `define PMEM_AWIDTH      15
515
  `define PMEM_SIZE     52224
516
`endif
517
`ifdef PMEM_SIZE_48_KB
518
  `define PMEM_AWIDTH      15
519
  `define PMEM_SIZE     49152
520
`endif
521
`ifdef PMEM_SIZE_41_KB
522
  `define PMEM_AWIDTH      15
523
  `define PMEM_SIZE     41984
524
`endif
525
`ifdef PMEM_SIZE_32_KB
526
  `define PMEM_AWIDTH      14
527
  `define PMEM_SIZE     32768
528
`endif
529
`ifdef PMEM_SIZE_24_KB
530
  `define PMEM_AWIDTH      14
531
  `define PMEM_SIZE     24576
532
`endif
533
`ifdef PMEM_SIZE_16_KB
534
  `define PMEM_AWIDTH      13
535
  `define PMEM_SIZE     16384
536
`endif
537
`ifdef PMEM_SIZE_12_KB
538
  `define PMEM_AWIDTH      13
539
  `define PMEM_SIZE     12288
540
`endif
541
`ifdef PMEM_SIZE_8_KB
542
  `define PMEM_AWIDTH      12
543
  `define PMEM_SIZE      8192
544
`endif
545
`ifdef PMEM_SIZE_4_KB
546
  `define PMEM_AWIDTH      11
547
  `define PMEM_SIZE      4096
548
`endif
549
`ifdef PMEM_SIZE_2_KB
550
  `define PMEM_AWIDTH      10
551
  `define PMEM_SIZE      2048
552
`endif
553
`ifdef PMEM_SIZE_1_KB
554
  `define PMEM_AWIDTH       9
555
  `define PMEM_SIZE      1024
556
`endif
557 151 olivier.gi
`ifdef PMEM_SIZE_CUSTOM
558
  `define PMEM_AWIDTH       `PMEM_CUSTOM_AWIDTH
559
  `define PMEM_SIZE         `PMEM_CUSTOM_SIZE
560
`endif
561 72 olivier.gi
 
562
// Data Memory Size
563
`ifdef DMEM_SIZE_32_KB
564
  `define DMEM_AWIDTH       14
565
  `define DMEM_SIZE      32768
566
`endif
567
`ifdef DMEM_SIZE_24_KB
568
  `define DMEM_AWIDTH       14
569
  `define DMEM_SIZE      24576
570
`endif
571
`ifdef DMEM_SIZE_16_KB
572
  `define DMEM_AWIDTH       13
573
  `define DMEM_SIZE      16384
574
`endif
575
`ifdef DMEM_SIZE_10_KB
576
  `define DMEM_AWIDTH       13
577
  `define DMEM_SIZE      10240
578
`endif
579
`ifdef DMEM_SIZE_8_KB
580
  `define DMEM_AWIDTH       12
581
  `define DMEM_SIZE       8192
582
`endif
583
`ifdef DMEM_SIZE_5_KB
584
  `define DMEM_AWIDTH       12
585
  `define DMEM_SIZE       5120
586
`endif
587
`ifdef DMEM_SIZE_4_KB
588
  `define DMEM_AWIDTH       11
589
  `define DMEM_SIZE       4096
590
`endif
591
`ifdef DMEM_SIZE_2p5_KB
592
  `define DMEM_AWIDTH       11
593
  `define DMEM_SIZE       2560
594
`endif
595
`ifdef DMEM_SIZE_2_KB
596
  `define DMEM_AWIDTH       10
597
  `define DMEM_SIZE       2048
598
`endif
599
`ifdef DMEM_SIZE_1_KB
600
  `define DMEM_AWIDTH        9
601
  `define DMEM_SIZE       1024
602
`endif
603
`ifdef DMEM_SIZE_512_B
604
  `define DMEM_AWIDTH        8
605
  `define DMEM_SIZE        512
606
`endif
607
`ifdef DMEM_SIZE_256_B
608
  `define DMEM_AWIDTH        7
609
  `define DMEM_SIZE        256
610
`endif
611
`ifdef DMEM_SIZE_128_B
612
  `define DMEM_AWIDTH        6
613
  `define DMEM_SIZE        128
614
`endif
615 151 olivier.gi
`ifdef DMEM_SIZE_CUSTOM
616
  `define DMEM_AWIDTH       `DMEM_CUSTOM_AWIDTH
617
  `define DMEM_SIZE         `DMEM_CUSTOM_SIZE
618
`endif
619 72 olivier.gi
 
620 111 olivier.gi
// Peripheral Memory Size
621
`ifdef PER_SIZE_32_KB
622
  `define PER_AWIDTH        14
623
  `define PER_SIZE       32768
624
`endif
625
`ifdef PER_SIZE_16_KB
626
  `define PER_AWIDTH        13
627
  `define PER_SIZE       16384
628
`endif
629
`ifdef PER_SIZE_8_KB
630
  `define PER_AWIDTH        12
631
  `define PER_SIZE        8192
632
`endif
633
`ifdef PER_SIZE_4_KB
634
  `define PER_AWIDTH        11
635
  `define PER_SIZE        4096
636
`endif
637
`ifdef PER_SIZE_2_KB
638
  `define PER_AWIDTH        10
639
  `define PER_SIZE        2048
640
`endif
641
`ifdef PER_SIZE_1_KB
642
  `define PER_AWIDTH         9
643
  `define PER_SIZE        1024
644
`endif
645
`ifdef PER_SIZE_512_B
646
  `define PER_AWIDTH         8
647
  `define PER_SIZE         512
648
`endif
649 151 olivier.gi
`ifdef PER_SIZE_CUSTOM
650
  `define PER_AWIDTH        `PER_CUSTOM_AWIDTH
651
  `define PER_SIZE          `PER_CUSTOM_SIZE
652
`endif
653 111 olivier.gi
 
654 33 olivier.gi
// Data Memory Base Adresses
655 111 olivier.gi
`define DMEM_BASE  `PER_SIZE
656 2 olivier.gi
 
657 33 olivier.gi
// Program & Data Memory most significant address bit (for 16 bit words)
658
`define PMEM_MSB   `PMEM_AWIDTH-1
659
`define DMEM_MSB   `DMEM_AWIDTH-1
660 111 olivier.gi
`define PER_MSB    `PER_AWIDTH-1
661 2 olivier.gi
 
662 193 olivier.gi
// Number of available IRQs
663
`ifdef  IRQ_16
664
`define IRQ_NR 16
665
`endif
666
`ifdef  IRQ_32
667
`define IRQ_NR 32
668
`define IRQ_NR_GE_32
669
`endif
670
`ifdef  IRQ_64
671
`define IRQ_NR 64
672
`define IRQ_NR_GE_32
673
`endif
674
 
675 72 olivier.gi
//
676
// STATES, REGISTER FIELDS, ...
677
//======================================
678 2 olivier.gi
 
679
// Instructions type
680
`define INST_SO  0
681
`define INST_JMP 1
682
`define INST_TO  2
683
 
684
// Single-operand arithmetic
685
`define RRC    0
686
`define SWPB   1
687
`define RRA    2
688
`define SXT    3
689
`define PUSH   4
690
`define CALL   5
691
`define RETI   6
692
`define IRQ    7
693
 
694
// Conditional jump
695
`define JNE    0
696
`define JEQ    1
697
`define JNC    2
698
`define JC     3
699
`define JN     4
700
`define JGE    5
701
`define JL     6
702
`define JMP    7
703
 
704
// Two-operand arithmetic
705
`define MOV    0
706
`define ADD    1
707
`define ADDC   2
708
`define SUBC   3
709
`define SUB    4
710
`define CMP    5
711
`define DADD   6
712
`define BIT    7
713
`define BIC    8
714
`define BIS    9
715
`define XOR   10
716
`define AND   11
717
 
718
// Addressing modes
719
`define DIR      0
720
`define IDX      1
721
`define INDIR    2
722
`define INDIR_I  3
723
`define SYMB     4
724
`define IMM      5
725
`define ABS      6
726
`define CONST    7
727
 
728 111 olivier.gi
// Instruction state machine
729
`define I_IRQ_FETCH 3'h0
730
`define I_IRQ_DONE  3'h1
731
`define I_DEC       3'h2
732
`define I_EXT1      3'h3
733
`define I_EXT2      3'h4
734
`define I_IDLE      3'h5
735
 
736 2 olivier.gi
// Execution state machine
737 136 olivier.gi
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
738
`define E_IRQ_0     4'h2
739 111 olivier.gi
`define E_IRQ_1     4'h1
740 136 olivier.gi
`define E_IRQ_2     4'h0
741 111 olivier.gi
`define E_IRQ_3     4'h3
742
`define E_IRQ_4     4'h4
743
`define E_SRC_AD    4'h5
744
`define E_SRC_RD    4'h6
745
`define E_SRC_WR    4'h7
746
`define E_DST_AD    4'h8
747
`define E_DST_RD    4'h9
748
`define E_DST_WR    4'hA
749
`define E_EXEC      4'hB
750
`define E_JUMP      4'hC
751
`define E_IDLE      4'hD
752 2 olivier.gi
 
753
// ALU control signals
754
`define ALU_SRC_INV   0
755
`define ALU_INC       1
756
`define ALU_INC_C     2
757
`define ALU_ADD       3
758
`define ALU_AND       4
759
`define ALU_OR        5
760
`define ALU_XOR       6
761
`define ALU_DADD      7
762
`define ALU_STAT_7    8
763
`define ALU_STAT_F    9
764
`define ALU_SHIFT    10
765
`define EXEC_NO_WR   11
766
 
767
// Debug interface
768
`define DBG_UART_WR   18
769
`define DBG_UART_BW   17
770
`define DBG_UART_ADDR 16:11
771
 
772
// Debug interface CPU_CTL register
773
`define HALT        0
774
`define RUN         1
775
`define ISTEP       2
776
`define SW_BRK_EN   3
777
`define FRZ_BRK_EN  4
778
`define RST_BRK_EN  5
779
`define CPU_RST     6
780
 
781
// Debug interface CPU_STAT register
782
`define HALT_RUN    0
783
`define PUC_PND     1
784
`define SWBRK_PND   3
785
`define HWBRK0_PND  4
786
`define HWBRK1_PND  5
787
 
788
// Debug interface BRKx_CTL register
789
`define BRK_MODE_RD 0
790
`define BRK_MODE_WR 1
791
`define BRK_MODE    1:0
792
`define BRK_EN      2
793
`define BRK_I_EN    3
794
`define BRK_RANGE   4
795
 
796
// Basic clock module: BCSCTL1 Control Register
797
`define DIVAx       5:4
798 202 olivier.gi
`define DMA_CPUOFF  0
799 204 olivier.gi
`define DMA_OSCOFF  1
800
`define DMA_SCG0    2
801
`define DMA_SCG1    3
802 2 olivier.gi
 
803
// Basic clock module: BCSCTL2 Control Register
804 136 olivier.gi
`define SELMx       7
805
`define DIVMx       5:4
806 2 olivier.gi
`define SELS        3
807
`define DIVSx       2:1
808
 
809 136 olivier.gi
// MCLK Clock gate
810
`ifdef CPUOFF_EN
811
  `define MCLK_CGATE
812
`else
813
`ifdef MCLK_DIVIDER
814
  `define MCLK_CGATE
815
`endif
816
`endif
817 2 olivier.gi
 
818 136 olivier.gi
// SMCLK Clock gate
819
`ifdef SCG1_EN
820
  `define SMCLK_CGATE
821
`else
822
`ifdef SMCLK_DIVIDER
823
  `define SMCLK_CGATE
824
`endif
825
`endif
826
 
827 2 olivier.gi
//
828
// DEBUG INTERFACE EXTRA CONFIGURATION
829
//======================================
830
 
831 111 olivier.gi
// Debug interface: CPU version
832 202 olivier.gi
//   1 - FPGA support only (Pre-BSD licence era)
833
//   2 - Add ASIC support
834
//   3 - Add DMA interface support
835
`define CPU_VERSION   3'h3
836 111 olivier.gi
 
837 2 olivier.gi
// Debug interface: Software breakpoint opcode
838
`define DBG_SWBRK_OP 16'h4343
839
 
840
// Debug UART interface auto data synchronization
841
// If the following define is commented out, then
842
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
843
// defined.
844
`define DBG_UART_AUTO_SYNC
845
 
846
// Debug UART interface data rate
847
//      In order to properly setup the UART debug interface, you
848
//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
849
//      the chosen BAUD rate from the UART interface.
850
//
851
//`define DBG_UART_BAUD    9600
852
//`define DBG_UART_BAUD   19200
853
//`define DBG_UART_BAUD   38400
854
//`define DBG_UART_BAUD   57600
855
//`define DBG_UART_BAUD  115200
856
//`define DBG_UART_BAUD  230400
857
//`define DBG_UART_BAUD  460800
858
//`define DBG_UART_BAUD  576000
859
//`define DBG_UART_BAUD  921600
860
`define DBG_UART_BAUD 2000000
861
`define DBG_DCO_FREQ  20000000
862
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
863
 
864 136 olivier.gi
// Debug interface input synchronizer
865
`define SYNC_DBG_UART_RXD
866
 
867 59 olivier.gi
// Enable/Disable the hardware breakpoint RANGE mode
868 111 olivier.gi
`ifdef DBG_HWBRK_RANGE
869
 `define HWBRK_RANGE 1'b1
870
`else
871
 `define HWBRK_RANGE 1'b0
872
`endif
873 59 olivier.gi
 
874 74 olivier.gi
// Counter width for the debug interface UART
875
`define DBG_UART_XFER_CNT_W 16
876
 
877 2 olivier.gi
// Check configuration
878
`ifdef DBG_EN
879
 `ifdef DBG_UART
880 155 olivier.gi
   `ifdef DBG_I2C
881
CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
882 2 olivier.gi
   `endif
883
 `else
884 155 olivier.gi
   `ifdef DBG_I2C
885 2 olivier.gi
   `else
886 155 olivier.gi
CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
887 2 olivier.gi
   `endif
888
 `endif
889
`endif
890 71 olivier.gi
 
891
//
892
// MULTIPLIER CONFIGURATION
893
//======================================
894
 
895
// If uncommented, the following define selects
896
// the 16x16 multiplier (1 cycle) instead of the
897
// default 16x8 multplier (2 cycles)
898
//`define MPY_16x16
899 202 olivier.gi
 
900 136 olivier.gi
//======================================
901
// CONFIGURATION CHECKS
902
//======================================
903 193 olivier.gi
 
904
`ifdef  IRQ_16
905
  `ifdef  IRQ_32
906
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
907
  `endif
908
  `ifdef  IRQ_64
909
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
910
  `endif
911
`endif
912
`ifdef  IRQ_32
913
  `ifdef  IRQ_64
914
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
915
  `endif
916
`endif
917 136 olivier.gi
`ifdef LFXT_DOMAIN
918
`else
919
 `ifdef MCLK_MUX
920
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
921
 `endif
922
 `ifdef SMCLK_MUX
923
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
924 202 olivier.gi
 `endif
925 136 olivier.gi
 `ifdef WATCHDOG_MUX
926
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
927
 `else
928
   `ifdef WATCHDOG_NOMUX_ACLK
929
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
930
   `endif
931
 `endif
932
 `ifdef OSCOFF_EN
933
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
934 202 olivier.gi
 `endif
935 136 olivier.gi
`endif

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