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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Blame information for rev 155

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1 2 olivier.gi
//----------------------------------------------------------------------------
2 136 olivier.gi
// Copyright (C) 2009 , Olivier Girard
3 2 olivier.gi
//
4 136 olivier.gi
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15 2 olivier.gi
//
16 136 olivier.gi
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27 2 olivier.gi
//
28
//----------------------------------------------------------------------------
29
// 
30 23 olivier.gi
// *File Name: openMSP430_defines.v
31 2 olivier.gi
// 
32
// *Module Description:
33
//                      openMSP430 Configuration file
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39 17 olivier.gi
// $Rev: 155 $
40
// $LastChangedBy: olivier.girard $
41
// $LastChangedDate: 2012-10-15 23:35:05 +0200 (Mon, 15 Oct 2012) $
42
//----------------------------------------------------------------------------
43 104 olivier.gi
//`define OMSP_NO_INCLUDE
44
`ifdef OMSP_NO_INCLUDE
45
`else
46 33 olivier.gi
`include "openMSP430_undefines.v"
47 104 olivier.gi
`endif
48 2 olivier.gi
 
49 111 olivier.gi
//============================================================================
50
//============================================================================
51
// BASIC SYSTEM CONFIGURATION
52
//============================================================================
53
//============================================================================
54 72 olivier.gi
//
55 111 olivier.gi
// Note: the sum of program, data and peripheral memory spaces must not
56
//      exceed 64 kB
57 72 olivier.gi
//
58 2 olivier.gi
 
59 33 olivier.gi
// Program Memory Size:
60 72 olivier.gi
//                     Uncomment the required memory size
61
//-------------------------------------------------------
62 151 olivier.gi
//`define PMEM_SIZE_CUSTOM
63 72 olivier.gi
//`define PMEM_SIZE_59_KB
64
//`define PMEM_SIZE_55_KB
65
//`define PMEM_SIZE_54_KB
66
//`define PMEM_SIZE_51_KB
67
//`define PMEM_SIZE_48_KB
68
//`define PMEM_SIZE_41_KB
69
//`define PMEM_SIZE_32_KB
70
//`define PMEM_SIZE_24_KB
71
//`define PMEM_SIZE_16_KB
72
//`define PMEM_SIZE_12_KB
73
//`define PMEM_SIZE_8_KB
74
`define PMEM_SIZE_4_KB
75
//`define PMEM_SIZE_2_KB
76
//`define PMEM_SIZE_1_KB
77 2 olivier.gi
 
78 111 olivier.gi
 
79 33 olivier.gi
// Data Memory Size:
80 72 olivier.gi
//                     Uncomment the required memory size
81
//-------------------------------------------------------
82 151 olivier.gi
//`define DMEM_SIZE_CUSTOM
83 72 olivier.gi
//`define DMEM_SIZE_32_KB
84
//`define DMEM_SIZE_24_KB
85
//`define DMEM_SIZE_16_KB
86
//`define DMEM_SIZE_10_KB
87
//`define DMEM_SIZE_8_KB
88
//`define DMEM_SIZE_5_KB
89
//`define DMEM_SIZE_4_KB
90
//`define DMEM_SIZE_2p5_KB
91
//`define DMEM_SIZE_2_KB
92
`define DMEM_SIZE_1_KB
93
//`define DMEM_SIZE_512_B
94
//`define DMEM_SIZE_256_B
95
//`define DMEM_SIZE_128_B
96 2 olivier.gi
 
97 111 olivier.gi
 
98 71 olivier.gi
// Include/Exclude Hardware Multiplier
99
`define MULTIPLIER
100
 
101
 
102 111 olivier.gi
// Include/Exclude Serial Debug interface
103 2 olivier.gi
`define DBG_EN
104
 
105 111 olivier.gi
 
106
//============================================================================
107
//============================================================================
108
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
109
//============================================================================
110
//============================================================================
111
 
112
//-------------------------------------------------------
113 136 olivier.gi
// Custom user version number
114
//-------------------------------------------------------
115
// This 5 bit field can be freely used in order to allow
116
// custom identification of the system through the debug
117
// interface.
118
// (see CPU_ID.USER_VERSION field in the documentation)
119
//-------------------------------------------------------
120
`define USER_VERSION 5'b00001
121
 
122
 
123
//-------------------------------------------------------
124
// Include/Exclude Watchdog timer
125
//-------------------------------------------------------
126
// When excluded, the following functionality will be
127
// lost:
128
//        - Watchog (both interval and watchdog modes)
129
//        - NMI interrupt edge selection
130
//        - Possibility to generate a software PUC reset
131
//-------------------------------------------------------
132
`define WATCHDOG
133
 
134
 
135
///-------------------------------------------------------
136
// Include/Exclude Non-Maskable-Interrupt support
137
//-------------------------------------------------------
138
`define NMI
139
 
140
 
141
//-------------------------------------------------------
142
// Input synchronizers
143
//-------------------------------------------------------
144
// In some cases, the asynchronous input ports might
145
// already be synchronized externally.
146
// If an extensive CDC design review showed that this
147
// is really the case,  the individual synchronizers
148
// can be disabled with the following defines.
149
//
150
// Notes:
151
//        - all three signals are all sampled in the MCLK domain
152
//
153
//        - the dbg_en signal reset the debug interface
154
//         when 0. Therefore make sure it is glitch free.
155
//
156
//-------------------------------------------------------
157
`define SYNC_NMI
158
`define SYNC_CPU_EN
159
`define SYNC_DBG_EN
160
 
161
 
162
//-------------------------------------------------------
163 111 olivier.gi
// Peripheral Memory Space:
164
//-------------------------------------------------------
165
// The original MSP430 architecture map the peripherals
166
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
167
// The following defines allow you to expand this space
168
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
169
// As a consequence, the data memory mapping will be
170
// shifted up and a custom linker script will therefore
171
// be required by the GCC compiler.
172
//-------------------------------------------------------
173 151 olivier.gi
//`define PER_SIZE_CUSTOM
174 111 olivier.gi
//`define PER_SIZE_32_KB
175
//`define PER_SIZE_16_KB
176
//`define PER_SIZE_8_KB
177
//`define PER_SIZE_4_KB
178
//`define PER_SIZE_2_KB
179
//`define PER_SIZE_1_KB
180
`define PER_SIZE_512_B
181
 
182
 
183
//-------------------------------------------------------
184
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
185
// (CPU break on PUC reset)
186
//-------------------------------------------------------
187
// When defined, the CPU will automatically break after
188 136 olivier.gi
// a PUC occurrence by default. This is typically useful
189 111 olivier.gi
// when the program memory can only be initialized through
190
// the serial debug interface.
191
//-------------------------------------------------------
192
//`define DBG_RST_BRK_EN
193
 
194
 
195
//============================================================================
196
//============================================================================
197
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
198
//============================================================================
199
//============================================================================
200 2 olivier.gi
//
201 111 olivier.gi
// IMPORTANT NOTE:  Please update following configuration options ONLY if
202
//                 you have a good reason to do so... and if you know what
203
//                 you are doing :-P
204
//
205
//============================================================================
206 2 olivier.gi
 
207 111 olivier.gi
//-------------------------------------------------------
208 155 olivier.gi
// Select serial debug interface protocol
209
//-------------------------------------------------------
210
//    DBG_UART -> Enable UART (8N1) debug interface
211
//    DBG_I2C  -> Enable I2C debug interface
212
//-------------------------------------------------------
213
`define DBG_UART
214
//`define DBG_I2C
215
 
216
 
217
//-------------------------------------------------------
218
// Enable the I2C broadcast address
219
//-------------------------------------------------------
220
// For multicore systems, a common I2C broadcast address
221
// can be given to all oMSP cores in order to
222
// synchronously RESET, START, STOP, or STEP all CPUs
223
// at once with a single I2C command.
224
// If you have a single openMSP430 in your system,
225
// this option can stay commented-out.
226
//-------------------------------------------------------
227
//`define DBG_I2C_BROADCAST
228
 
229
 
230
//-------------------------------------------------------
231 136 olivier.gi
// Number of hardware breakpoint/watchpoint units
232
// (each unit contains two hardware addresses available
233
// for breakpoints or watchpoints):
234 111 olivier.gi
//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
235
//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
236
//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
237
//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
238
//-------------------------------------------------------
239
// Please keep in mind that hardware breakpoints only
240
// make sense whenever the program memory is not an SRAM
241
// (i.e. Flash/OTP/ROM/...) or when you are interested
242 136 olivier.gi
// in data breakpoints.
243 111 olivier.gi
//-------------------------------------------------------
244 2 olivier.gi
`define  DBG_HWBRK_0
245 37 olivier.gi
//`define  DBG_HWBRK_1
246
//`define  DBG_HWBRK_2
247
//`define  DBG_HWBRK_3
248 2 olivier.gi
 
249
 
250 111 olivier.gi
//-------------------------------------------------------
251
// Enable/Disable the hardware breakpoint RANGE mode
252
//-------------------------------------------------------
253
// When enabled this feature allows the hardware breakpoint
254
// units to stop the cpu whenever an instruction or data
255
// access lays within an address range.
256
// Note that this feature is not supported by GDB.
257
//-------------------------------------------------------
258
//`define DBG_HWBRK_RANGE
259
 
260
 
261
//-------------------------------------------------------
262 151 olivier.gi
// Custom Program/Data and Peripheral Memory Spaces
263
//-------------------------------------------------------
264
// The following values are valid only if the
265
// corresponding *_SIZE_CUSTOM defines are uncommented:
266
//
267
//  - *_SIZE   : size of the section in bytes.
268
//  - *_AWIDTH : address port width, this value must allow
269
//               to address all WORDS of the section
270
//               (i.e. the *_SIZE divided by 2)
271
//-------------------------------------------------------
272
 
273
// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
274
`define PMEM_CUSTOM_AWIDTH      10
275
`define PMEM_CUSTOM_SIZE      2048
276
 
277
// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
278
`define DMEM_CUSTOM_AWIDTH       6
279
`define DMEM_CUSTOM_SIZE       128
280
 
281
// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
282
`define PER_CUSTOM_AWIDTH        8
283
`define PER_CUSTOM_SIZE        512
284
 
285
 
286
//-------------------------------------------------------
287 136 olivier.gi
// ASIC version
288 111 olivier.gi
//-------------------------------------------------------
289 136 olivier.gi
// When uncommented, this define will enable the
290
// ASIC system configuration section (see below) and
291
// will activate scan support for production test.
292 109 olivier.gi
//
293 136 olivier.gi
// WARNING: if you target an FPGA, leave this define
294
//          commented.
295 111 olivier.gi
//-------------------------------------------------------
296 136 olivier.gi
//`define ASIC
297 109 olivier.gi
 
298
 
299 136 olivier.gi
//============================================================================
300
//============================================================================
301
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
302
//============================================================================
303
//============================================================================
304
`ifdef ASIC
305 111 olivier.gi
 
306 136 olivier.gi
//===============================================================
307
// FINE GRAINED CLOCK GATING
308
//===============================================================
309
 
310
//-------------------------------------------------------
311
// When uncommented, this define will enable the fine
312
// grained clock gating of all registers in the core.
313
//-------------------------------------------------------
314
`define CLOCK_GATING
315
 
316
 
317
//===============================================================
318
// LFXT CLOCK DOMAIN
319
//===============================================================
320
 
321
//-------------------------------------------------------
322
// When uncommented, this define will enable the lfxt_clk
323
// clock domain.
324
// When commented out, the whole chip is clocked with dco_clk.
325
//-------------------------------------------------------
326
`define LFXT_DOMAIN
327
 
328
 
329
//===============================================================
330
// CLOCK MUXES
331
//===============================================================
332
 
333
//-------------------------------------------------------
334
// MCLK: Clock Mux
335
//-------------------------------------------------------
336
// When uncommented, this define will enable the
337
// MCLK clock MUX allowing the selection between
338
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
339
// When commented, DCO_CLK is selected.
340
//-------------------------------------------------------
341
`define MCLK_MUX
342
 
343
//-------------------------------------------------------
344
// SMCLK: Clock Mux
345
//-------------------------------------------------------
346
// When uncommented, this define will enable the
347
// SMCLK clock MUX allowing the selection between
348
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
349
// When commented, DCO_CLK is selected.
350
//-------------------------------------------------------
351
`define SMCLK_MUX
352
 
353
//-------------------------------------------------------
354
// WATCHDOG: Clock Mux
355
//-------------------------------------------------------
356
// When uncommented, this define will enable the
357
// Watchdog clock MUX allowing the selection between
358
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
359
// When commented out, ACLK is selected if the
360
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
361
// selected otherwise.
362
//-------------------------------------------------------
363
`define WATCHDOG_MUX
364
//`define WATCHDOG_NOMUX_ACLK
365
 
366
 
367
//===============================================================
368
// CLOCK DIVIDERS
369
//===============================================================
370
 
371
//-------------------------------------------------------
372
// MCLK: Clock divider
373
//-------------------------------------------------------
374
// When uncommented, this define will enable the
375
// MCLK clock divider (/1/2/4/8)
376
//-------------------------------------------------------
377
`define MCLK_DIVIDER
378
 
379
//-------------------------------------------------------
380
// SMCLK: Clock divider (/1/2/4/8)
381
//-------------------------------------------------------
382
// When uncommented, this define will enable the
383
// SMCLK clock divider
384
//-------------------------------------------------------
385
`define SMCLK_DIVIDER
386
 
387
//-------------------------------------------------------
388
// ACLK: Clock divider (/1/2/4/8)
389
//-------------------------------------------------------
390
// When uncommented, this define will enable the
391
// ACLK clock divider
392
//-------------------------------------------------------
393
`define ACLK_DIVIDER
394
 
395
 
396
//===============================================================
397
// LOW POWER MODES
398
//===============================================================
399
 
400
//-------------------------------------------------------
401
// LOW POWER MODE: CPUOFF
402
//-------------------------------------------------------
403
// When uncommented, this define will include the
404
// clock gate allowing to switch off MCLK in
405
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
406
//-------------------------------------------------------
407
`define CPUOFF_EN
408
 
409
//-------------------------------------------------------
410
// LOW POWER MODE: SCG0
411
//-------------------------------------------------------
412
// When uncommented, this define will enable the
413
// DCO_ENABLE/WKUP port control (always 1 when commented).
414
// This allows to switch off the DCO oscillator in the
415
// following low power modes: LPM1, LPM3, LPM4
416
//-------------------------------------------------------
417
`define SCG0_EN
418
 
419
//-------------------------------------------------------
420
// LOW POWER MODE: SCG1
421
//-------------------------------------------------------
422
// When uncommented, this define will include the
423
// clock gate allowing to switch off SMCLK in
424
// the following low power modes: LPM2, LPM3, LPM4
425
//-------------------------------------------------------
426
`define SCG1_EN
427
 
428
//-------------------------------------------------------
429
// LOW POWER MODE: OSCOFF
430
//-------------------------------------------------------
431
// When uncommented, this define will include the
432
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
433
// port control (always 1 when commented).
434
// This allows to switch off the low frequency oscillator
435
// in the following low power modes: LPM4
436
//-------------------------------------------------------
437
`define OSCOFF_EN
438
 
439
 
440
 
441
`endif
442
 
443 2 olivier.gi
//==========================================================================//
444
//==========================================================================//
445
//==========================================================================//
446
//==========================================================================//
447
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
448
//==========================================================================//
449
//==========================================================================//
450
//==========================================================================//
451
//==========================================================================//
452
 
453 72 olivier.gi
//
454 111 olivier.gi
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
455
//==================================================
456 2 olivier.gi
 
457 72 olivier.gi
// Program Memory Size
458
`ifdef PMEM_SIZE_59_KB
459
  `define PMEM_AWIDTH      15
460
  `define PMEM_SIZE     60416
461
`endif
462
`ifdef PMEM_SIZE_55_KB
463
  `define PMEM_AWIDTH      15
464
  `define PMEM_SIZE     56320
465
`endif
466
`ifdef PMEM_SIZE_54_KB
467
  `define PMEM_AWIDTH      15
468
  `define PMEM_SIZE     55296
469
`endif
470
`ifdef PMEM_SIZE_51_KB
471
  `define PMEM_AWIDTH      15
472
  `define PMEM_SIZE     52224
473
`endif
474
`ifdef PMEM_SIZE_48_KB
475
  `define PMEM_AWIDTH      15
476
  `define PMEM_SIZE     49152
477
`endif
478
`ifdef PMEM_SIZE_41_KB
479
  `define PMEM_AWIDTH      15
480
  `define PMEM_SIZE     41984
481
`endif
482
`ifdef PMEM_SIZE_32_KB
483
  `define PMEM_AWIDTH      14
484
  `define PMEM_SIZE     32768
485
`endif
486
`ifdef PMEM_SIZE_24_KB
487
  `define PMEM_AWIDTH      14
488
  `define PMEM_SIZE     24576
489
`endif
490
`ifdef PMEM_SIZE_16_KB
491
  `define PMEM_AWIDTH      13
492
  `define PMEM_SIZE     16384
493
`endif
494
`ifdef PMEM_SIZE_12_KB
495
  `define PMEM_AWIDTH      13
496
  `define PMEM_SIZE     12288
497
`endif
498
`ifdef PMEM_SIZE_8_KB
499
  `define PMEM_AWIDTH      12
500
  `define PMEM_SIZE      8192
501
`endif
502
`ifdef PMEM_SIZE_4_KB
503
  `define PMEM_AWIDTH      11
504
  `define PMEM_SIZE      4096
505
`endif
506
`ifdef PMEM_SIZE_2_KB
507
  `define PMEM_AWIDTH      10
508
  `define PMEM_SIZE      2048
509
`endif
510
`ifdef PMEM_SIZE_1_KB
511
  `define PMEM_AWIDTH       9
512
  `define PMEM_SIZE      1024
513
`endif
514 151 olivier.gi
`ifdef PMEM_SIZE_CUSTOM
515
  `define PMEM_AWIDTH       `PMEM_CUSTOM_AWIDTH
516
  `define PMEM_SIZE         `PMEM_CUSTOM_SIZE
517
`endif
518 72 olivier.gi
 
519
// Data Memory Size
520
`ifdef DMEM_SIZE_32_KB
521
  `define DMEM_AWIDTH       14
522
  `define DMEM_SIZE      32768
523
`endif
524
`ifdef DMEM_SIZE_24_KB
525
  `define DMEM_AWIDTH       14
526
  `define DMEM_SIZE      24576
527
`endif
528
`ifdef DMEM_SIZE_16_KB
529
  `define DMEM_AWIDTH       13
530
  `define DMEM_SIZE      16384
531
`endif
532
`ifdef DMEM_SIZE_10_KB
533
  `define DMEM_AWIDTH       13
534
  `define DMEM_SIZE      10240
535
`endif
536
`ifdef DMEM_SIZE_8_KB
537
  `define DMEM_AWIDTH       12
538
  `define DMEM_SIZE       8192
539
`endif
540
`ifdef DMEM_SIZE_5_KB
541
  `define DMEM_AWIDTH       12
542
  `define DMEM_SIZE       5120
543
`endif
544
`ifdef DMEM_SIZE_4_KB
545
  `define DMEM_AWIDTH       11
546
  `define DMEM_SIZE       4096
547
`endif
548
`ifdef DMEM_SIZE_2p5_KB
549
  `define DMEM_AWIDTH       11
550
  `define DMEM_SIZE       2560
551
`endif
552
`ifdef DMEM_SIZE_2_KB
553
  `define DMEM_AWIDTH       10
554
  `define DMEM_SIZE       2048
555
`endif
556
`ifdef DMEM_SIZE_1_KB
557
  `define DMEM_AWIDTH        9
558
  `define DMEM_SIZE       1024
559
`endif
560
`ifdef DMEM_SIZE_512_B
561
  `define DMEM_AWIDTH        8
562
  `define DMEM_SIZE        512
563
`endif
564
`ifdef DMEM_SIZE_256_B
565
  `define DMEM_AWIDTH        7
566
  `define DMEM_SIZE        256
567
`endif
568
`ifdef DMEM_SIZE_128_B
569
  `define DMEM_AWIDTH        6
570
  `define DMEM_SIZE        128
571
`endif
572 151 olivier.gi
`ifdef DMEM_SIZE_CUSTOM
573
  `define DMEM_AWIDTH       `DMEM_CUSTOM_AWIDTH
574
  `define DMEM_SIZE         `DMEM_CUSTOM_SIZE
575
`endif
576 72 olivier.gi
 
577 111 olivier.gi
// Peripheral Memory Size
578
`ifdef PER_SIZE_32_KB
579
  `define PER_AWIDTH        14
580
  `define PER_SIZE       32768
581
`endif
582
`ifdef PER_SIZE_16_KB
583
  `define PER_AWIDTH        13
584
  `define PER_SIZE       16384
585
`endif
586
`ifdef PER_SIZE_8_KB
587
  `define PER_AWIDTH        12
588
  `define PER_SIZE        8192
589
`endif
590
`ifdef PER_SIZE_4_KB
591
  `define PER_AWIDTH        11
592
  `define PER_SIZE        4096
593
`endif
594
`ifdef PER_SIZE_2_KB
595
  `define PER_AWIDTH        10
596
  `define PER_SIZE        2048
597
`endif
598
`ifdef PER_SIZE_1_KB
599
  `define PER_AWIDTH         9
600
  `define PER_SIZE        1024
601
`endif
602
`ifdef PER_SIZE_512_B
603
  `define PER_AWIDTH         8
604
  `define PER_SIZE         512
605
`endif
606 151 olivier.gi
`ifdef PER_SIZE_CUSTOM
607
  `define PER_AWIDTH        `PER_CUSTOM_AWIDTH
608
  `define PER_SIZE          `PER_CUSTOM_SIZE
609
`endif
610 111 olivier.gi
 
611 33 olivier.gi
// Data Memory Base Adresses
612 111 olivier.gi
`define DMEM_BASE  `PER_SIZE
613 2 olivier.gi
 
614 33 olivier.gi
// Program & Data Memory most significant address bit (for 16 bit words)
615
`define PMEM_MSB   `PMEM_AWIDTH-1
616
`define DMEM_MSB   `DMEM_AWIDTH-1
617 111 olivier.gi
`define PER_MSB    `PER_AWIDTH-1
618 2 olivier.gi
 
619 72 olivier.gi
//
620
// STATES, REGISTER FIELDS, ...
621
//======================================
622 2 olivier.gi
 
623
// Instructions type
624
`define INST_SO  0
625
`define INST_JMP 1
626
`define INST_TO  2
627
 
628
// Single-operand arithmetic
629
`define RRC    0
630
`define SWPB   1
631
`define RRA    2
632
`define SXT    3
633
`define PUSH   4
634
`define CALL   5
635
`define RETI   6
636
`define IRQ    7
637
 
638
// Conditional jump
639
`define JNE    0
640
`define JEQ    1
641
`define JNC    2
642
`define JC     3
643
`define JN     4
644
`define JGE    5
645
`define JL     6
646
`define JMP    7
647
 
648
// Two-operand arithmetic
649
`define MOV    0
650
`define ADD    1
651
`define ADDC   2
652
`define SUBC   3
653
`define SUB    4
654
`define CMP    5
655
`define DADD   6
656
`define BIT    7
657
`define BIC    8
658
`define BIS    9
659
`define XOR   10
660
`define AND   11
661
 
662
// Addressing modes
663
`define DIR      0
664
`define IDX      1
665
`define INDIR    2
666
`define INDIR_I  3
667
`define SYMB     4
668
`define IMM      5
669
`define ABS      6
670
`define CONST    7
671
 
672 111 olivier.gi
// Instruction state machine
673
`define I_IRQ_FETCH 3'h0
674
`define I_IRQ_DONE  3'h1
675
`define I_DEC       3'h2
676
`define I_EXT1      3'h3
677
`define I_EXT2      3'h4
678
`define I_IDLE      3'h5
679
 
680 2 olivier.gi
// Execution state machine
681 136 olivier.gi
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
682
`define E_IRQ_0     4'h2
683 111 olivier.gi
`define E_IRQ_1     4'h1
684 136 olivier.gi
`define E_IRQ_2     4'h0
685 111 olivier.gi
`define E_IRQ_3     4'h3
686
`define E_IRQ_4     4'h4
687
`define E_SRC_AD    4'h5
688
`define E_SRC_RD    4'h6
689
`define E_SRC_WR    4'h7
690
`define E_DST_AD    4'h8
691
`define E_DST_RD    4'h9
692
`define E_DST_WR    4'hA
693
`define E_EXEC      4'hB
694
`define E_JUMP      4'hC
695
`define E_IDLE      4'hD
696 2 olivier.gi
 
697
// ALU control signals
698
`define ALU_SRC_INV   0
699
`define ALU_INC       1
700
`define ALU_INC_C     2
701
`define ALU_ADD       3
702
`define ALU_AND       4
703
`define ALU_OR        5
704
`define ALU_XOR       6
705
`define ALU_DADD      7
706
`define ALU_STAT_7    8
707
`define ALU_STAT_F    9
708
`define ALU_SHIFT    10
709
`define EXEC_NO_WR   11
710
 
711
// Debug interface
712
`define DBG_UART_WR   18
713
`define DBG_UART_BW   17
714
`define DBG_UART_ADDR 16:11
715
 
716
// Debug interface CPU_CTL register
717
`define HALT        0
718
`define RUN         1
719
`define ISTEP       2
720
`define SW_BRK_EN   3
721
`define FRZ_BRK_EN  4
722
`define RST_BRK_EN  5
723
`define CPU_RST     6
724
 
725
// Debug interface CPU_STAT register
726
`define HALT_RUN    0
727
`define PUC_PND     1
728
`define SWBRK_PND   3
729
`define HWBRK0_PND  4
730
`define HWBRK1_PND  5
731
 
732
// Debug interface BRKx_CTL register
733
`define BRK_MODE_RD 0
734
`define BRK_MODE_WR 1
735
`define BRK_MODE    1:0
736
`define BRK_EN      2
737
`define BRK_I_EN    3
738
`define BRK_RANGE   4
739
 
740
// Basic clock module: BCSCTL1 Control Register
741
`define DIVAx       5:4
742
 
743
// Basic clock module: BCSCTL2 Control Register
744 136 olivier.gi
`define SELMx       7
745
`define DIVMx       5:4
746 2 olivier.gi
`define SELS        3
747
`define DIVSx       2:1
748
 
749 136 olivier.gi
// MCLK Clock gate
750
`ifdef CPUOFF_EN
751
  `define MCLK_CGATE
752
`else
753
`ifdef MCLK_DIVIDER
754
  `define MCLK_CGATE
755
`endif
756
`endif
757 2 olivier.gi
 
758 136 olivier.gi
// SMCLK Clock gate
759
`ifdef SCG1_EN
760
  `define SMCLK_CGATE
761
`else
762
`ifdef SMCLK_DIVIDER
763
  `define SMCLK_CGATE
764
`endif
765
`endif
766
 
767 2 olivier.gi
//
768
// DEBUG INTERFACE EXTRA CONFIGURATION
769
//======================================
770
 
771 111 olivier.gi
// Debug interface: CPU version
772 136 olivier.gi
`define CPU_VERSION   3'h2
773 111 olivier.gi
 
774 2 olivier.gi
// Debug interface: Software breakpoint opcode
775
`define DBG_SWBRK_OP 16'h4343
776
 
777
// Debug UART interface auto data synchronization
778
// If the following define is commented out, then
779
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
780
// defined.
781
`define DBG_UART_AUTO_SYNC
782
 
783
// Debug UART interface data rate
784
//      In order to properly setup the UART debug interface, you
785
//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
786
//      the chosen BAUD rate from the UART interface.
787
//
788
//`define DBG_UART_BAUD    9600
789
//`define DBG_UART_BAUD   19200
790
//`define DBG_UART_BAUD   38400
791
//`define DBG_UART_BAUD   57600
792
//`define DBG_UART_BAUD  115200
793
//`define DBG_UART_BAUD  230400
794
//`define DBG_UART_BAUD  460800
795
//`define DBG_UART_BAUD  576000
796
//`define DBG_UART_BAUD  921600
797
`define DBG_UART_BAUD 2000000
798
`define DBG_DCO_FREQ  20000000
799
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
800
 
801 136 olivier.gi
// Debug interface input synchronizer
802
`define SYNC_DBG_UART_RXD
803
 
804 59 olivier.gi
// Enable/Disable the hardware breakpoint RANGE mode
805 111 olivier.gi
`ifdef DBG_HWBRK_RANGE
806
 `define HWBRK_RANGE 1'b1
807
`else
808
 `define HWBRK_RANGE 1'b0
809
`endif
810 59 olivier.gi
 
811 74 olivier.gi
// Counter width for the debug interface UART
812
`define DBG_UART_XFER_CNT_W 16
813
 
814 2 olivier.gi
// Check configuration
815
`ifdef DBG_EN
816
 `ifdef DBG_UART
817 155 olivier.gi
   `ifdef DBG_I2C
818
CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
819 2 olivier.gi
   `endif
820
 `else
821 155 olivier.gi
   `ifdef DBG_I2C
822 2 olivier.gi
   `else
823 155 olivier.gi
CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
824 2 olivier.gi
   `endif
825
 `endif
826
`endif
827 71 olivier.gi
 
828
//
829
// MULTIPLIER CONFIGURATION
830
//======================================
831
 
832
// If uncommented, the following define selects
833
// the 16x16 multiplier (1 cycle) instead of the
834
// default 16x8 multplier (2 cycles)
835
//`define MPY_16x16
836 136 olivier.gi
 
837
//======================================
838
// CONFIGURATION CHECKS
839
//======================================
840
`ifdef LFXT_DOMAIN
841
`else
842
 `ifdef MCLK_MUX
843
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
844
 `endif
845
 `ifdef SMCLK_MUX
846
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
847
 `endif
848
 `ifdef WATCHDOG_MUX
849
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
850
 `else
851
   `ifdef WATCHDOG_NOMUX_ACLK
852
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
853
   `endif
854
 `endif
855
 `ifdef OSCOFF_EN
856
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
857
 `endif
858
`endif

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