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//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430_defines.v
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//
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// *Module Description:
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// openMSP430 Configuration file
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 155 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-10-15 23:35:05 +0200 (Mon, 15 Oct 2012) $
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//----------------------------------------------------------------------------
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olivier.gi |
//`define OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_undefines.v"
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`endif
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//============================================================================
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//============================================================================
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// BASIC SYSTEM CONFIGURATION
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//============================================================================
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//============================================================================
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//
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// Note: the sum of program, data and peripheral memory spaces must not
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// exceed 64 kB
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//
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// Program Memory Size:
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// Uncomment the required memory size
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//-------------------------------------------------------
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//`define PMEM_SIZE_CUSTOM
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//`define PMEM_SIZE_59_KB
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//`define PMEM_SIZE_55_KB
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//`define PMEM_SIZE_54_KB
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//`define PMEM_SIZE_51_KB
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//`define PMEM_SIZE_48_KB
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//`define PMEM_SIZE_41_KB
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//`define PMEM_SIZE_32_KB
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//`define PMEM_SIZE_24_KB
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//`define PMEM_SIZE_16_KB
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//`define PMEM_SIZE_12_KB
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//`define PMEM_SIZE_8_KB
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`define PMEM_SIZE_4_KB
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//`define PMEM_SIZE_2_KB
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//`define PMEM_SIZE_1_KB
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// Data Memory Size:
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// Uncomment the required memory size
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//-------------------------------------------------------
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//`define DMEM_SIZE_CUSTOM
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//`define DMEM_SIZE_32_KB
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//`define DMEM_SIZE_24_KB
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//`define DMEM_SIZE_16_KB
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//`define DMEM_SIZE_10_KB
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//`define DMEM_SIZE_8_KB
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//`define DMEM_SIZE_5_KB
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//`define DMEM_SIZE_4_KB
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//`define DMEM_SIZE_2p5_KB
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//`define DMEM_SIZE_2_KB
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`define DMEM_SIZE_1_KB
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//`define DMEM_SIZE_512_B
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//`define DMEM_SIZE_256_B
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//`define DMEM_SIZE_128_B
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// Include/Exclude Hardware Multiplier
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`define MULTIPLIER
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// Include/Exclude Serial Debug interface
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`define DBG_EN
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//============================================================================
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//============================================================================
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// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
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//============================================================================
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//============================================================================
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//-------------------------------------------------------
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// Custom user version number
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//-------------------------------------------------------
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// This 5 bit field can be freely used in order to allow
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// custom identification of the system through the debug
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// interface.
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// (see CPU_ID.USER_VERSION field in the documentation)
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//-------------------------------------------------------
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`define USER_VERSION 5'b00001
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//-------------------------------------------------------
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// Include/Exclude Watchdog timer
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//-------------------------------------------------------
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// When excluded, the following functionality will be
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// lost:
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// - Watchog (both interval and watchdog modes)
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// - NMI interrupt edge selection
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// - Possibility to generate a software PUC reset
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//-------------------------------------------------------
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`define WATCHDOG
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///-------------------------------------------------------
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// Include/Exclude Non-Maskable-Interrupt support
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//-------------------------------------------------------
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`define NMI
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//-------------------------------------------------------
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// Input synchronizers
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//-------------------------------------------------------
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// In some cases, the asynchronous input ports might
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// already be synchronized externally.
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// If an extensive CDC design review showed that this
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// is really the case, the individual synchronizers
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// can be disabled with the following defines.
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//
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// Notes:
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// - all three signals are all sampled in the MCLK domain
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//
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// - the dbg_en signal reset the debug interface
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// when 0. Therefore make sure it is glitch free.
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//
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//-------------------------------------------------------
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`define SYNC_NMI
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`define SYNC_CPU_EN
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`define SYNC_DBG_EN
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//-------------------------------------------------------
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// Peripheral Memory Space:
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//-------------------------------------------------------
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// The original MSP430 architecture map the peripherals
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// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
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// The following defines allow you to expand this space
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// up to 32 kB (i.e. from 0x0000 to 0x7fff).
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// As a consequence, the data memory mapping will be
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// shifted up and a custom linker script will therefore
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// be required by the GCC compiler.
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//-------------------------------------------------------
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//`define PER_SIZE_CUSTOM
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//`define PER_SIZE_32_KB
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//`define PER_SIZE_16_KB
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//`define PER_SIZE_8_KB
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//`define PER_SIZE_4_KB
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//`define PER_SIZE_2_KB
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//`define PER_SIZE_1_KB
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`define PER_SIZE_512_B
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//-------------------------------------------------------
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// Defines the debugger CPU_CTL.RST_BRK_EN reset value
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// (CPU break on PUC reset)
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//-------------------------------------------------------
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// When defined, the CPU will automatically break after
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// a PUC occurrence by default. This is typically useful
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// when the program memory can only be initialized through
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// the serial debug interface.
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//-------------------------------------------------------
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//`define DBG_RST_BRK_EN
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//============================================================================
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//============================================================================
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// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
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//============================================================================
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//============================================================================
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//
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// IMPORTANT NOTE: Please update following configuration options ONLY if
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// you have a good reason to do so... and if you know what
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// you are doing :-P
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//
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//============================================================================
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//-------------------------------------------------------
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// Select serial debug interface protocol
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//-------------------------------------------------------
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// DBG_UART -> Enable UART (8N1) debug interface
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// DBG_I2C -> Enable I2C debug interface
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//-------------------------------------------------------
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`define DBG_UART
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//`define DBG_I2C
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//-------------------------------------------------------
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// Enable the I2C broadcast address
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//-------------------------------------------------------
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// For multicore systems, a common I2C broadcast address
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// can be given to all oMSP cores in order to
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// synchronously RESET, START, STOP, or STEP all CPUs
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// at once with a single I2C command.
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// If you have a single openMSP430 in your system,
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// this option can stay commented-out.
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//-------------------------------------------------------
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//`define DBG_I2C_BROADCAST
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//-------------------------------------------------------
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// Number of hardware breakpoint/watchpoint units
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// (each unit contains two hardware addresses available
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// for breakpoints or watchpoints):
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olivier.gi |
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
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// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
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// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
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// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
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//-------------------------------------------------------
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// Please keep in mind that hardware breakpoints only
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// make sense whenever the program memory is not an SRAM
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// (i.e. Flash/OTP/ROM/...) or when you are interested
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olivier.gi |
// in data breakpoints.
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//-------------------------------------------------------
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`define DBG_HWBRK_0
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//`define DBG_HWBRK_1
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//`define DBG_HWBRK_2
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//`define DBG_HWBRK_3
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olivier.gi |
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olivier.gi |
//-------------------------------------------------------
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// Enable/Disable the hardware breakpoint RANGE mode
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252 |
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//-------------------------------------------------------
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// When enabled this feature allows the hardware breakpoint
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// units to stop the cpu whenever an instruction or data
|
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// access lays within an address range.
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// Note that this feature is not supported by GDB.
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//-------------------------------------------------------
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//`define DBG_HWBRK_RANGE
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|
260 |
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//-------------------------------------------------------
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olivier.gi |
// Custom Program/Data and Peripheral Memory Spaces
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//-------------------------------------------------------
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// The following values are valid only if the
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// corresponding *_SIZE_CUSTOM defines are uncommented:
|
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//
|
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// - *_SIZE : size of the section in bytes.
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// - *_AWIDTH : address port width, this value must allow
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// to address all WORDS of the section
|
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// (i.e. the *_SIZE divided by 2)
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//-------------------------------------------------------
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// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
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`define PMEM_CUSTOM_AWIDTH 10
|
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`define PMEM_CUSTOM_SIZE 2048
|
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|
277 |
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// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)
|
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`define DMEM_CUSTOM_AWIDTH 6
|
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`define DMEM_CUSTOM_SIZE 128
|
280 |
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|
281 |
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// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
|
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`define PER_CUSTOM_AWIDTH 8
|
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`define PER_CUSTOM_SIZE 512
|
284 |
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|
285 |
|
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|
286 |
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//-------------------------------------------------------
|
287 |
136 |
olivier.gi |
// ASIC version
|
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olivier.gi |
//-------------------------------------------------------
|
289 |
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olivier.gi |
// When uncommented, this define will enable the
|
290 |
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// ASIC system configuration section (see below) and
|
291 |
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// will activate scan support for production test.
|
292 |
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//
|
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olivier.gi |
// WARNING: if you target an FPGA, leave this define
|
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// commented.
|
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olivier.gi |
//-------------------------------------------------------
|
296 |
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olivier.gi |
//`define ASIC
|
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109 |
olivier.gi |
|
298 |
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|
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olivier.gi |
//============================================================================
|
300 |
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//============================================================================
|
301 |
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// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
|
302 |
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//============================================================================
|
303 |
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//============================================================================
|
304 |
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`ifdef ASIC
|
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|
306 |
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olivier.gi |
//===============================================================
|
307 |
|
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// FINE GRAINED CLOCK GATING
|
308 |
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//===============================================================
|
309 |
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|
310 |
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//-------------------------------------------------------
|
311 |
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// When uncommented, this define will enable the fine
|
312 |
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// grained clock gating of all registers in the core.
|
313 |
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//-------------------------------------------------------
|
314 |
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`define CLOCK_GATING
|
315 |
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|
316 |
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|
317 |
|
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//===============================================================
|
318 |
|
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// LFXT CLOCK DOMAIN
|
319 |
|
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//===============================================================
|
320 |
|
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|
321 |
|
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//-------------------------------------------------------
|
322 |
|
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// When uncommented, this define will enable the lfxt_clk
|
323 |
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// clock domain.
|
324 |
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// When commented out, the whole chip is clocked with dco_clk.
|
325 |
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//-------------------------------------------------------
|
326 |
|
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`define LFXT_DOMAIN
|
327 |
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|
328 |
|
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|
329 |
|
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//===============================================================
|
330 |
|
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// CLOCK MUXES
|
331 |
|
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//===============================================================
|
332 |
|
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|
333 |
|
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//-------------------------------------------------------
|
334 |
|
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// MCLK: Clock Mux
|
335 |
|
|
//-------------------------------------------------------
|
336 |
|
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// When uncommented, this define will enable the
|
337 |
|
|
// MCLK clock MUX allowing the selection between
|
338 |
|
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// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
|
339 |
|
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// When commented, DCO_CLK is selected.
|
340 |
|
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//-------------------------------------------------------
|
341 |
|
|
`define MCLK_MUX
|
342 |
|
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|
343 |
|
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//-------------------------------------------------------
|
344 |
|
|
// SMCLK: Clock Mux
|
345 |
|
|
//-------------------------------------------------------
|
346 |
|
|
// When uncommented, this define will enable the
|
347 |
|
|
// SMCLK clock MUX allowing the selection between
|
348 |
|
|
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
|
349 |
|
|
// When commented, DCO_CLK is selected.
|
350 |
|
|
//-------------------------------------------------------
|
351 |
|
|
`define SMCLK_MUX
|
352 |
|
|
|
353 |
|
|
//-------------------------------------------------------
|
354 |
|
|
// WATCHDOG: Clock Mux
|
355 |
|
|
//-------------------------------------------------------
|
356 |
|
|
// When uncommented, this define will enable the
|
357 |
|
|
// Watchdog clock MUX allowing the selection between
|
358 |
|
|
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
|
359 |
|
|
// When commented out, ACLK is selected if the
|
360 |
|
|
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
|
361 |
|
|
// selected otherwise.
|
362 |
|
|
//-------------------------------------------------------
|
363 |
|
|
`define WATCHDOG_MUX
|
364 |
|
|
//`define WATCHDOG_NOMUX_ACLK
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
//===============================================================
|
368 |
|
|
// CLOCK DIVIDERS
|
369 |
|
|
//===============================================================
|
370 |
|
|
|
371 |
|
|
//-------------------------------------------------------
|
372 |
|
|
// MCLK: Clock divider
|
373 |
|
|
//-------------------------------------------------------
|
374 |
|
|
// When uncommented, this define will enable the
|
375 |
|
|
// MCLK clock divider (/1/2/4/8)
|
376 |
|
|
//-------------------------------------------------------
|
377 |
|
|
`define MCLK_DIVIDER
|
378 |
|
|
|
379 |
|
|
//-------------------------------------------------------
|
380 |
|
|
// SMCLK: Clock divider (/1/2/4/8)
|
381 |
|
|
//-------------------------------------------------------
|
382 |
|
|
// When uncommented, this define will enable the
|
383 |
|
|
// SMCLK clock divider
|
384 |
|
|
//-------------------------------------------------------
|
385 |
|
|
`define SMCLK_DIVIDER
|
386 |
|
|
|
387 |
|
|
//-------------------------------------------------------
|
388 |
|
|
// ACLK: Clock divider (/1/2/4/8)
|
389 |
|
|
//-------------------------------------------------------
|
390 |
|
|
// When uncommented, this define will enable the
|
391 |
|
|
// ACLK clock divider
|
392 |
|
|
//-------------------------------------------------------
|
393 |
|
|
`define ACLK_DIVIDER
|
394 |
|
|
|
395 |
|
|
|
396 |
|
|
//===============================================================
|
397 |
|
|
// LOW POWER MODES
|
398 |
|
|
//===============================================================
|
399 |
|
|
|
400 |
|
|
//-------------------------------------------------------
|
401 |
|
|
// LOW POWER MODE: CPUOFF
|
402 |
|
|
//-------------------------------------------------------
|
403 |
|
|
// When uncommented, this define will include the
|
404 |
|
|
// clock gate allowing to switch off MCLK in
|
405 |
|
|
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
|
406 |
|
|
//-------------------------------------------------------
|
407 |
|
|
`define CPUOFF_EN
|
408 |
|
|
|
409 |
|
|
//-------------------------------------------------------
|
410 |
|
|
// LOW POWER MODE: SCG0
|
411 |
|
|
//-------------------------------------------------------
|
412 |
|
|
// When uncommented, this define will enable the
|
413 |
|
|
// DCO_ENABLE/WKUP port control (always 1 when commented).
|
414 |
|
|
// This allows to switch off the DCO oscillator in the
|
415 |
|
|
// following low power modes: LPM1, LPM3, LPM4
|
416 |
|
|
//-------------------------------------------------------
|
417 |
|
|
`define SCG0_EN
|
418 |
|
|
|
419 |
|
|
//-------------------------------------------------------
|
420 |
|
|
// LOW POWER MODE: SCG1
|
421 |
|
|
//-------------------------------------------------------
|
422 |
|
|
// When uncommented, this define will include the
|
423 |
|
|
// clock gate allowing to switch off SMCLK in
|
424 |
|
|
// the following low power modes: LPM2, LPM3, LPM4
|
425 |
|
|
//-------------------------------------------------------
|
426 |
|
|
`define SCG1_EN
|
427 |
|
|
|
428 |
|
|
//-------------------------------------------------------
|
429 |
|
|
// LOW POWER MODE: OSCOFF
|
430 |
|
|
//-------------------------------------------------------
|
431 |
|
|
// When uncommented, this define will include the
|
432 |
|
|
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
|
433 |
|
|
// port control (always 1 when commented).
|
434 |
|
|
// This allows to switch off the low frequency oscillator
|
435 |
|
|
// in the following low power modes: LPM4
|
436 |
|
|
//-------------------------------------------------------
|
437 |
|
|
`define OSCOFF_EN
|
438 |
|
|
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
`endif
|
442 |
|
|
|
443 |
2 |
olivier.gi |
//==========================================================================//
|
444 |
|
|
//==========================================================================//
|
445 |
|
|
//==========================================================================//
|
446 |
|
|
//==========================================================================//
|
447 |
|
|
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
|
448 |
|
|
//==========================================================================//
|
449 |
|
|
//==========================================================================//
|
450 |
|
|
//==========================================================================//
|
451 |
|
|
//==========================================================================//
|
452 |
|
|
|
453 |
72 |
olivier.gi |
//
|
454 |
111 |
olivier.gi |
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
|
455 |
|
|
//==================================================
|
456 |
2 |
olivier.gi |
|
457 |
72 |
olivier.gi |
// Program Memory Size
|
458 |
|
|
`ifdef PMEM_SIZE_59_KB
|
459 |
|
|
`define PMEM_AWIDTH 15
|
460 |
|
|
`define PMEM_SIZE 60416
|
461 |
|
|
`endif
|
462 |
|
|
`ifdef PMEM_SIZE_55_KB
|
463 |
|
|
`define PMEM_AWIDTH 15
|
464 |
|
|
`define PMEM_SIZE 56320
|
465 |
|
|
`endif
|
466 |
|
|
`ifdef PMEM_SIZE_54_KB
|
467 |
|
|
`define PMEM_AWIDTH 15
|
468 |
|
|
`define PMEM_SIZE 55296
|
469 |
|
|
`endif
|
470 |
|
|
`ifdef PMEM_SIZE_51_KB
|
471 |
|
|
`define PMEM_AWIDTH 15
|
472 |
|
|
`define PMEM_SIZE 52224
|
473 |
|
|
`endif
|
474 |
|
|
`ifdef PMEM_SIZE_48_KB
|
475 |
|
|
`define PMEM_AWIDTH 15
|
476 |
|
|
`define PMEM_SIZE 49152
|
477 |
|
|
`endif
|
478 |
|
|
`ifdef PMEM_SIZE_41_KB
|
479 |
|
|
`define PMEM_AWIDTH 15
|
480 |
|
|
`define PMEM_SIZE 41984
|
481 |
|
|
`endif
|
482 |
|
|
`ifdef PMEM_SIZE_32_KB
|
483 |
|
|
`define PMEM_AWIDTH 14
|
484 |
|
|
`define PMEM_SIZE 32768
|
485 |
|
|
`endif
|
486 |
|
|
`ifdef PMEM_SIZE_24_KB
|
487 |
|
|
`define PMEM_AWIDTH 14
|
488 |
|
|
`define PMEM_SIZE 24576
|
489 |
|
|
`endif
|
490 |
|
|
`ifdef PMEM_SIZE_16_KB
|
491 |
|
|
`define PMEM_AWIDTH 13
|
492 |
|
|
`define PMEM_SIZE 16384
|
493 |
|
|
`endif
|
494 |
|
|
`ifdef PMEM_SIZE_12_KB
|
495 |
|
|
`define PMEM_AWIDTH 13
|
496 |
|
|
`define PMEM_SIZE 12288
|
497 |
|
|
`endif
|
498 |
|
|
`ifdef PMEM_SIZE_8_KB
|
499 |
|
|
`define PMEM_AWIDTH 12
|
500 |
|
|
`define PMEM_SIZE 8192
|
501 |
|
|
`endif
|
502 |
|
|
`ifdef PMEM_SIZE_4_KB
|
503 |
|
|
`define PMEM_AWIDTH 11
|
504 |
|
|
`define PMEM_SIZE 4096
|
505 |
|
|
`endif
|
506 |
|
|
`ifdef PMEM_SIZE_2_KB
|
507 |
|
|
`define PMEM_AWIDTH 10
|
508 |
|
|
`define PMEM_SIZE 2048
|
509 |
|
|
`endif
|
510 |
|
|
`ifdef PMEM_SIZE_1_KB
|
511 |
|
|
`define PMEM_AWIDTH 9
|
512 |
|
|
`define PMEM_SIZE 1024
|
513 |
|
|
`endif
|
514 |
151 |
olivier.gi |
`ifdef PMEM_SIZE_CUSTOM
|
515 |
|
|
`define PMEM_AWIDTH `PMEM_CUSTOM_AWIDTH
|
516 |
|
|
`define PMEM_SIZE `PMEM_CUSTOM_SIZE
|
517 |
|
|
`endif
|
518 |
72 |
olivier.gi |
|
519 |
|
|
// Data Memory Size
|
520 |
|
|
`ifdef DMEM_SIZE_32_KB
|
521 |
|
|
`define DMEM_AWIDTH 14
|
522 |
|
|
`define DMEM_SIZE 32768
|
523 |
|
|
`endif
|
524 |
|
|
`ifdef DMEM_SIZE_24_KB
|
525 |
|
|
`define DMEM_AWIDTH 14
|
526 |
|
|
`define DMEM_SIZE 24576
|
527 |
|
|
`endif
|
528 |
|
|
`ifdef DMEM_SIZE_16_KB
|
529 |
|
|
`define DMEM_AWIDTH 13
|
530 |
|
|
`define DMEM_SIZE 16384
|
531 |
|
|
`endif
|
532 |
|
|
`ifdef DMEM_SIZE_10_KB
|
533 |
|
|
`define DMEM_AWIDTH 13
|
534 |
|
|
`define DMEM_SIZE 10240
|
535 |
|
|
`endif
|
536 |
|
|
`ifdef DMEM_SIZE_8_KB
|
537 |
|
|
`define DMEM_AWIDTH 12
|
538 |
|
|
`define DMEM_SIZE 8192
|
539 |
|
|
`endif
|
540 |
|
|
`ifdef DMEM_SIZE_5_KB
|
541 |
|
|
`define DMEM_AWIDTH 12
|
542 |
|
|
`define DMEM_SIZE 5120
|
543 |
|
|
`endif
|
544 |
|
|
`ifdef DMEM_SIZE_4_KB
|
545 |
|
|
`define DMEM_AWIDTH 11
|
546 |
|
|
`define DMEM_SIZE 4096
|
547 |
|
|
`endif
|
548 |
|
|
`ifdef DMEM_SIZE_2p5_KB
|
549 |
|
|
`define DMEM_AWIDTH 11
|
550 |
|
|
`define DMEM_SIZE 2560
|
551 |
|
|
`endif
|
552 |
|
|
`ifdef DMEM_SIZE_2_KB
|
553 |
|
|
`define DMEM_AWIDTH 10
|
554 |
|
|
`define DMEM_SIZE 2048
|
555 |
|
|
`endif
|
556 |
|
|
`ifdef DMEM_SIZE_1_KB
|
557 |
|
|
`define DMEM_AWIDTH 9
|
558 |
|
|
`define DMEM_SIZE 1024
|
559 |
|
|
`endif
|
560 |
|
|
`ifdef DMEM_SIZE_512_B
|
561 |
|
|
`define DMEM_AWIDTH 8
|
562 |
|
|
`define DMEM_SIZE 512
|
563 |
|
|
`endif
|
564 |
|
|
`ifdef DMEM_SIZE_256_B
|
565 |
|
|
`define DMEM_AWIDTH 7
|
566 |
|
|
`define DMEM_SIZE 256
|
567 |
|
|
`endif
|
568 |
|
|
`ifdef DMEM_SIZE_128_B
|
569 |
|
|
`define DMEM_AWIDTH 6
|
570 |
|
|
`define DMEM_SIZE 128
|
571 |
|
|
`endif
|
572 |
151 |
olivier.gi |
`ifdef DMEM_SIZE_CUSTOM
|
573 |
|
|
`define DMEM_AWIDTH `DMEM_CUSTOM_AWIDTH
|
574 |
|
|
`define DMEM_SIZE `DMEM_CUSTOM_SIZE
|
575 |
|
|
`endif
|
576 |
72 |
olivier.gi |
|
577 |
111 |
olivier.gi |
// Peripheral Memory Size
|
578 |
|
|
`ifdef PER_SIZE_32_KB
|
579 |
|
|
`define PER_AWIDTH 14
|
580 |
|
|
`define PER_SIZE 32768
|
581 |
|
|
`endif
|
582 |
|
|
`ifdef PER_SIZE_16_KB
|
583 |
|
|
`define PER_AWIDTH 13
|
584 |
|
|
`define PER_SIZE 16384
|
585 |
|
|
`endif
|
586 |
|
|
`ifdef PER_SIZE_8_KB
|
587 |
|
|
`define PER_AWIDTH 12
|
588 |
|
|
`define PER_SIZE 8192
|
589 |
|
|
`endif
|
590 |
|
|
`ifdef PER_SIZE_4_KB
|
591 |
|
|
`define PER_AWIDTH 11
|
592 |
|
|
`define PER_SIZE 4096
|
593 |
|
|
`endif
|
594 |
|
|
`ifdef PER_SIZE_2_KB
|
595 |
|
|
`define PER_AWIDTH 10
|
596 |
|
|
`define PER_SIZE 2048
|
597 |
|
|
`endif
|
598 |
|
|
`ifdef PER_SIZE_1_KB
|
599 |
|
|
`define PER_AWIDTH 9
|
600 |
|
|
`define PER_SIZE 1024
|
601 |
|
|
`endif
|
602 |
|
|
`ifdef PER_SIZE_512_B
|
603 |
|
|
`define PER_AWIDTH 8
|
604 |
|
|
`define PER_SIZE 512
|
605 |
|
|
`endif
|
606 |
151 |
olivier.gi |
`ifdef PER_SIZE_CUSTOM
|
607 |
|
|
`define PER_AWIDTH `PER_CUSTOM_AWIDTH
|
608 |
|
|
`define PER_SIZE `PER_CUSTOM_SIZE
|
609 |
|
|
`endif
|
610 |
111 |
olivier.gi |
|
611 |
33 |
olivier.gi |
// Data Memory Base Adresses
|
612 |
111 |
olivier.gi |
`define DMEM_BASE `PER_SIZE
|
613 |
2 |
olivier.gi |
|
614 |
33 |
olivier.gi |
// Program & Data Memory most significant address bit (for 16 bit words)
|
615 |
|
|
`define PMEM_MSB `PMEM_AWIDTH-1
|
616 |
|
|
`define DMEM_MSB `DMEM_AWIDTH-1
|
617 |
111 |
olivier.gi |
`define PER_MSB `PER_AWIDTH-1
|
618 |
2 |
olivier.gi |
|
619 |
72 |
olivier.gi |
//
|
620 |
|
|
// STATES, REGISTER FIELDS, ...
|
621 |
|
|
//======================================
|
622 |
2 |
olivier.gi |
|
623 |
|
|
// Instructions type
|
624 |
|
|
`define INST_SO 0
|
625 |
|
|
`define INST_JMP 1
|
626 |
|
|
`define INST_TO 2
|
627 |
|
|
|
628 |
|
|
// Single-operand arithmetic
|
629 |
|
|
`define RRC 0
|
630 |
|
|
`define SWPB 1
|
631 |
|
|
`define RRA 2
|
632 |
|
|
`define SXT 3
|
633 |
|
|
`define PUSH 4
|
634 |
|
|
`define CALL 5
|
635 |
|
|
`define RETI 6
|
636 |
|
|
`define IRQ 7
|
637 |
|
|
|
638 |
|
|
// Conditional jump
|
639 |
|
|
`define JNE 0
|
640 |
|
|
`define JEQ 1
|
641 |
|
|
`define JNC 2
|
642 |
|
|
`define JC 3
|
643 |
|
|
`define JN 4
|
644 |
|
|
`define JGE 5
|
645 |
|
|
`define JL 6
|
646 |
|
|
`define JMP 7
|
647 |
|
|
|
648 |
|
|
// Two-operand arithmetic
|
649 |
|
|
`define MOV 0
|
650 |
|
|
`define ADD 1
|
651 |
|
|
`define ADDC 2
|
652 |
|
|
`define SUBC 3
|
653 |
|
|
`define SUB 4
|
654 |
|
|
`define CMP 5
|
655 |
|
|
`define DADD 6
|
656 |
|
|
`define BIT 7
|
657 |
|
|
`define BIC 8
|
658 |
|
|
`define BIS 9
|
659 |
|
|
`define XOR 10
|
660 |
|
|
`define AND 11
|
661 |
|
|
|
662 |
|
|
// Addressing modes
|
663 |
|
|
`define DIR 0
|
664 |
|
|
`define IDX 1
|
665 |
|
|
`define INDIR 2
|
666 |
|
|
`define INDIR_I 3
|
667 |
|
|
`define SYMB 4
|
668 |
|
|
`define IMM 5
|
669 |
|
|
`define ABS 6
|
670 |
|
|
`define CONST 7
|
671 |
|
|
|
672 |
111 |
olivier.gi |
// Instruction state machine
|
673 |
|
|
`define I_IRQ_FETCH 3'h0
|
674 |
|
|
`define I_IRQ_DONE 3'h1
|
675 |
|
|
`define I_DEC 3'h2
|
676 |
|
|
`define I_EXT1 3'h3
|
677 |
|
|
`define I_EXT2 3'h4
|
678 |
|
|
`define I_IDLE 3'h5
|
679 |
|
|
|
680 |
2 |
olivier.gi |
// Execution state machine
|
681 |
136 |
olivier.gi |
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
|
682 |
|
|
`define E_IRQ_0 4'h2
|
683 |
111 |
olivier.gi |
`define E_IRQ_1 4'h1
|
684 |
136 |
olivier.gi |
`define E_IRQ_2 4'h0
|
685 |
111 |
olivier.gi |
`define E_IRQ_3 4'h3
|
686 |
|
|
`define E_IRQ_4 4'h4
|
687 |
|
|
`define E_SRC_AD 4'h5
|
688 |
|
|
`define E_SRC_RD 4'h6
|
689 |
|
|
`define E_SRC_WR 4'h7
|
690 |
|
|
`define E_DST_AD 4'h8
|
691 |
|
|
`define E_DST_RD 4'h9
|
692 |
|
|
`define E_DST_WR 4'hA
|
693 |
|
|
`define E_EXEC 4'hB
|
694 |
|
|
`define E_JUMP 4'hC
|
695 |
|
|
`define E_IDLE 4'hD
|
696 |
2 |
olivier.gi |
|
697 |
|
|
// ALU control signals
|
698 |
|
|
`define ALU_SRC_INV 0
|
699 |
|
|
`define ALU_INC 1
|
700 |
|
|
`define ALU_INC_C 2
|
701 |
|
|
`define ALU_ADD 3
|
702 |
|
|
`define ALU_AND 4
|
703 |
|
|
`define ALU_OR 5
|
704 |
|
|
`define ALU_XOR 6
|
705 |
|
|
`define ALU_DADD 7
|
706 |
|
|
`define ALU_STAT_7 8
|
707 |
|
|
`define ALU_STAT_F 9
|
708 |
|
|
`define ALU_SHIFT 10
|
709 |
|
|
`define EXEC_NO_WR 11
|
710 |
|
|
|
711 |
|
|
// Debug interface
|
712 |
|
|
`define DBG_UART_WR 18
|
713 |
|
|
`define DBG_UART_BW 17
|
714 |
|
|
`define DBG_UART_ADDR 16:11
|
715 |
|
|
|
716 |
|
|
// Debug interface CPU_CTL register
|
717 |
|
|
`define HALT 0
|
718 |
|
|
`define RUN 1
|
719 |
|
|
`define ISTEP 2
|
720 |
|
|
`define SW_BRK_EN 3
|
721 |
|
|
`define FRZ_BRK_EN 4
|
722 |
|
|
`define RST_BRK_EN 5
|
723 |
|
|
`define CPU_RST 6
|
724 |
|
|
|
725 |
|
|
// Debug interface CPU_STAT register
|
726 |
|
|
`define HALT_RUN 0
|
727 |
|
|
`define PUC_PND 1
|
728 |
|
|
`define SWBRK_PND 3
|
729 |
|
|
`define HWBRK0_PND 4
|
730 |
|
|
`define HWBRK1_PND 5
|
731 |
|
|
|
732 |
|
|
// Debug interface BRKx_CTL register
|
733 |
|
|
`define BRK_MODE_RD 0
|
734 |
|
|
`define BRK_MODE_WR 1
|
735 |
|
|
`define BRK_MODE 1:0
|
736 |
|
|
`define BRK_EN 2
|
737 |
|
|
`define BRK_I_EN 3
|
738 |
|
|
`define BRK_RANGE 4
|
739 |
|
|
|
740 |
|
|
// Basic clock module: BCSCTL1 Control Register
|
741 |
|
|
`define DIVAx 5:4
|
742 |
|
|
|
743 |
|
|
// Basic clock module: BCSCTL2 Control Register
|
744 |
136 |
olivier.gi |
`define SELMx 7
|
745 |
|
|
`define DIVMx 5:4
|
746 |
2 |
olivier.gi |
`define SELS 3
|
747 |
|
|
`define DIVSx 2:1
|
748 |
|
|
|
749 |
136 |
olivier.gi |
// MCLK Clock gate
|
750 |
|
|
`ifdef CPUOFF_EN
|
751 |
|
|
`define MCLK_CGATE
|
752 |
|
|
`else
|
753 |
|
|
`ifdef MCLK_DIVIDER
|
754 |
|
|
`define MCLK_CGATE
|
755 |
|
|
`endif
|
756 |
|
|
`endif
|
757 |
2 |
olivier.gi |
|
758 |
136 |
olivier.gi |
// SMCLK Clock gate
|
759 |
|
|
`ifdef SCG1_EN
|
760 |
|
|
`define SMCLK_CGATE
|
761 |
|
|
`else
|
762 |
|
|
`ifdef SMCLK_DIVIDER
|
763 |
|
|
`define SMCLK_CGATE
|
764 |
|
|
`endif
|
765 |
|
|
`endif
|
766 |
|
|
|
767 |
2 |
olivier.gi |
//
|
768 |
|
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
769 |
|
|
//======================================
|
770 |
|
|
|
771 |
111 |
olivier.gi |
// Debug interface: CPU version
|
772 |
136 |
olivier.gi |
`define CPU_VERSION 3'h2
|
773 |
111 |
olivier.gi |
|
774 |
2 |
olivier.gi |
// Debug interface: Software breakpoint opcode
|
775 |
|
|
`define DBG_SWBRK_OP 16'h4343
|
776 |
|
|
|
777 |
|
|
// Debug UART interface auto data synchronization
|
778 |
|
|
// If the following define is commented out, then
|
779 |
|
|
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
|
780 |
|
|
// defined.
|
781 |
|
|
`define DBG_UART_AUTO_SYNC
|
782 |
|
|
|
783 |
|
|
// Debug UART interface data rate
|
784 |
|
|
// In order to properly setup the UART debug interface, you
|
785 |
|
|
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
|
786 |
|
|
// the chosen BAUD rate from the UART interface.
|
787 |
|
|
//
|
788 |
|
|
//`define DBG_UART_BAUD 9600
|
789 |
|
|
//`define DBG_UART_BAUD 19200
|
790 |
|
|
//`define DBG_UART_BAUD 38400
|
791 |
|
|
//`define DBG_UART_BAUD 57600
|
792 |
|
|
//`define DBG_UART_BAUD 115200
|
793 |
|
|
//`define DBG_UART_BAUD 230400
|
794 |
|
|
//`define DBG_UART_BAUD 460800
|
795 |
|
|
//`define DBG_UART_BAUD 576000
|
796 |
|
|
//`define DBG_UART_BAUD 921600
|
797 |
|
|
`define DBG_UART_BAUD 2000000
|
798 |
|
|
`define DBG_DCO_FREQ 20000000
|
799 |
|
|
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
|
800 |
|
|
|
801 |
136 |
olivier.gi |
// Debug interface input synchronizer
|
802 |
|
|
`define SYNC_DBG_UART_RXD
|
803 |
|
|
|
804 |
59 |
olivier.gi |
// Enable/Disable the hardware breakpoint RANGE mode
|
805 |
111 |
olivier.gi |
`ifdef DBG_HWBRK_RANGE
|
806 |
|
|
`define HWBRK_RANGE 1'b1
|
807 |
|
|
`else
|
808 |
|
|
`define HWBRK_RANGE 1'b0
|
809 |
|
|
`endif
|
810 |
59 |
olivier.gi |
|
811 |
74 |
olivier.gi |
// Counter width for the debug interface UART
|
812 |
|
|
`define DBG_UART_XFER_CNT_W 16
|
813 |
|
|
|
814 |
2 |
olivier.gi |
// Check configuration
|
815 |
|
|
`ifdef DBG_EN
|
816 |
|
|
`ifdef DBG_UART
|
817 |
155 |
olivier.gi |
`ifdef DBG_I2C
|
818 |
|
|
CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
|
819 |
2 |
olivier.gi |
`endif
|
820 |
|
|
`else
|
821 |
155 |
olivier.gi |
`ifdef DBG_I2C
|
822 |
2 |
olivier.gi |
`else
|
823 |
155 |
olivier.gi |
CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
|
824 |
2 |
olivier.gi |
`endif
|
825 |
|
|
`endif
|
826 |
|
|
`endif
|
827 |
71 |
olivier.gi |
|
828 |
|
|
//
|
829 |
|
|
// MULTIPLIER CONFIGURATION
|
830 |
|
|
//======================================
|
831 |
|
|
|
832 |
|
|
// If uncommented, the following define selects
|
833 |
|
|
// the 16x16 multiplier (1 cycle) instead of the
|
834 |
|
|
// default 16x8 multplier (2 cycles)
|
835 |
|
|
//`define MPY_16x16
|
836 |
136 |
olivier.gi |
|
837 |
|
|
//======================================
|
838 |
|
|
// CONFIGURATION CHECKS
|
839 |
|
|
//======================================
|
840 |
|
|
`ifdef LFXT_DOMAIN
|
841 |
|
|
`else
|
842 |
|
|
`ifdef MCLK_MUX
|
843 |
|
|
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
844 |
|
|
`endif
|
845 |
|
|
`ifdef SMCLK_MUX
|
846 |
|
|
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
847 |
|
|
`endif
|
848 |
|
|
`ifdef WATCHDOG_MUX
|
849 |
|
|
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
850 |
|
|
`else
|
851 |
|
|
`ifdef WATCHDOG_NOMUX_ACLK
|
852 |
|
|
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
853 |
|
|
`endif
|
854 |
|
|
`endif
|
855 |
|
|
`ifdef OSCOFF_EN
|
856 |
|
|
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
857 |
|
|
`endif
|
858 |
|
|
`endif
|