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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [periph/] [omsp_timerA.v] - Blame information for rev 37

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1 2 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
//
25 34 olivier.gi
// *File Name: omsp_timerA.v
26 2 olivier.gi
// 
27
// *Module Description:
28
//                       Timer A top-level
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34 17 olivier.gi
// $Rev: 37 $
35
// $LastChangedBy: olivier.girard $
36
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
37
//----------------------------------------------------------------------------
38 23 olivier.gi
`include "timescale.v"
39
`include "openMSP430_defines.v"
40 2 olivier.gi
 
41 34 olivier.gi
module  omsp_timerA (
42 2 olivier.gi
 
43
// OUTPUTs
44
    irq_ta0,                        // Timer A interrupt: TACCR0
45
    irq_ta1,                        // Timer A interrupt: TAIV, TACCR1, TACCR2
46
    per_dout,                       // Peripheral data output
47
    ta_out0,                        // Timer A output 0
48
    ta_out0_en,                     // Timer A output 0 enable
49
    ta_out1,                        // Timer A output 1
50
    ta_out1_en,                     // Timer A output 1 enable
51
    ta_out2,                        // Timer A output 2
52
    ta_out2_en,                     // Timer A output 2 enable
53
 
54
// INPUTs
55
    aclk_en,                        // ACLK enable (from CPU)
56
    dbg_freeze,                     // Freeze Timer A counter
57
    inclk,                          // INCLK external timer clock (SLOW)
58
    irq_ta0_acc,                    // Interrupt request TACCR0 accepted
59
    mclk,                           // Main system clock
60
    per_addr,                       // Peripheral address
61
    per_din,                        // Peripheral data input
62
    per_en,                         // Peripheral enable (high active)
63
    per_wen,                        // Peripheral write enable (high active)
64
    puc,                            // Main system reset
65
    smclk_en,                       // SMCLK enable (from CPU)
66
    ta_cci0a,                       // Timer A capture 0 input A
67
    ta_cci0b,                       // Timer A capture 0 input B
68
    ta_cci1a,                       // Timer A capture 1 input A
69
    ta_cci1b,                       // Timer A capture 1 input B
70
    ta_cci2a,                       // Timer A capture 2 input A
71
    ta_cci2b,                       // Timer A capture 2 input B
72
    taclk                           // TACLK external timer clock (SLOW)
73
);
74
 
75
// OUTPUTs
76
//=========
77
output              irq_ta0;        // Timer A interrupt: TACCR0
78
output              irq_ta1;        // Timer A interrupt: TAIV, TACCR1, TACCR2
79
output       [15:0] per_dout;       // Peripheral data output
80
output              ta_out0;        // Timer A output 0
81
output              ta_out0_en;     // Timer A output 0 enable
82
output              ta_out1;        // Timer A output 1
83
output              ta_out1_en;     // Timer A output 1 enable
84
output              ta_out2;        // Timer A output 2
85
output              ta_out2_en;     // Timer A output 2 enable
86
 
87
// INPUTs
88
//=========
89
input               aclk_en;        // ACLK enable (from CPU)
90
input               dbg_freeze;     // Freeze Timer A counter
91
input               inclk;          // INCLK external timer clock (SLOW)
92
input               irq_ta0_acc;    // Interrupt request TACCR0 accepted
93
input               mclk;           // Main system clock
94
input         [7:0] per_addr;       // Peripheral address
95
input        [15:0] per_din;        // Peripheral data input
96
input               per_en;         // Peripheral enable (high active)
97
input         [1:0] per_wen;        // Peripheral write enable (high active)
98
input               puc;            // Main system reset
99
input               smclk_en;       // SMCLK enable (from CPU)
100
input               ta_cci0a;       // Timer A capture 0 input A
101
input               ta_cci0b;       // Timer A capture 0 input B
102
input               ta_cci1a;       // Timer A capture 1 input A
103
input               ta_cci1b;       // Timer A capture 1 input B
104
input               ta_cci2a;       // Timer A capture 2 input A
105
input               ta_cci2b;       // Timer A capture 2 input B
106
input               taclk;          // TACLK external timer clock (SLOW)
107
 
108
 
109
//=============================================================================
110
// 1)  PARAMETER DECLARATION
111
//=============================================================================
112
 
113
// Register addresses
114
parameter           TACTL      = 9'h160;
115
parameter           TAR        = 9'h170;
116
parameter           TACCTL0    = 9'h162;
117
parameter           TACCR0     = 9'h172;
118
parameter           TACCTL1    = 9'h164;
119
parameter           TACCR1     = 9'h174;
120
parameter           TACCTL2    = 9'h166;
121
parameter           TACCR2     = 9'h176;
122
parameter           TAIV       = 9'h12E;
123
 
124
 
125
// Register one-hot decoder
126
parameter           TACTL_D    = (512'h1 << TACTL);
127
parameter           TAR_D      = (512'h1 << TAR);
128
parameter           TACCTL0_D  = (512'h1 << TACCTL0);
129
parameter           TACCR0_D   = (512'h1 << TACCR0);
130
parameter           TACCTL1_D  = (512'h1 << TACCTL1);
131
parameter           TACCR1_D   = (512'h1 << TACCR1);
132
parameter           TACCTL2_D  = (512'h1 << TACCTL2);
133
parameter           TACCR2_D   = (512'h1 << TACCR2);
134
parameter           TAIV_D     = (512'h1 << TAIV);
135
 
136
 
137
//============================================================================
138
// 2)  REGISTER DECODER
139
//============================================================================
140
 
141
// Register address decode
142
reg  [511:0]  reg_dec;
143
always @(per_addr)
144
  case ({per_addr,1'b0})
145
    TACTL  :     reg_dec  =  TACTL_D;
146
    TAR    :     reg_dec  =  TAR_D;
147
    TACCTL0:     reg_dec  =  TACCTL0_D;
148
    TACCR0 :     reg_dec  =  TACCR0_D;
149
    TACCTL1:     reg_dec  =  TACCTL1_D;
150
    TACCR1 :     reg_dec  =  TACCR1_D;
151
    TACCTL2:     reg_dec  =  TACCTL2_D;
152
    TACCR2 :     reg_dec  =  TACCR2_D;
153
    TAIV   :     reg_dec  =  TAIV_D;
154
    default:     reg_dec  =  {512{1'b0}};
155
  endcase
156
 
157
// Read/Write probes
158
wire         reg_write =  |per_wen   & per_en;
159
wire         reg_read  = ~|per_wen   & per_en;
160
 
161
// Read/Write vectors
162
wire [511:0] reg_wr    = reg_dec & {512{reg_write}};
163
wire [511:0] reg_rd    = reg_dec & {512{reg_read}};
164
 
165
 
166
//============================================================================
167
// 3) REGISTERS
168
//============================================================================
169
 
170
// TACTL Register
171
//-----------------   
172
reg   [9:0] tactl;
173
 
174
wire        tactl_wr = reg_wr[TACTL];
175
wire        taclr    = tactl_wr & per_din[`TACLR];
176
wire        taifg_set;
177
wire        taifg_clr;
178
 
179
always @ (posedge mclk or posedge puc)
180
  if (puc)           tactl <=  10'h000;
181
  else if (tactl_wr) tactl <=  ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
182
  else               tactl <=  (tactl                    | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
183
 
184
 
185
// TAR Register
186
//-----------------   
187
reg  [15:0] tar;
188
 
189
wire        tar_wr = reg_wr[TAR];
190
 
191
wire        tar_clk;
192
wire        tar_clr;
193
wire        tar_inc;
194
wire        tar_dec;
195
wire [15:0] tar_add  = tar_inc ? 16'h0001 :
196
                       tar_dec ? 16'hffff : 16'h0000;
197
wire [15:0] tar_nxt  = tar_clr ? 16'h0000 : (tar+tar_add);
198
 
199
always @ (posedge mclk or posedge puc)
200
  if (puc)                         tar <=  16'h0000;
201
  else if  (tar_wr)                tar <=  per_din;
202
  else if  (taclr)                 tar <=  16'h0000;
203
  else if  (tar_clk & ~dbg_freeze) tar <=  tar_nxt;
204
 
205
 
206
// TACCTL0 Register
207
//------------------   
208
reg  [15:0] tacctl0;
209
 
210
wire        tacctl0_wr = reg_wr[TACCTL0];
211
wire        ccifg0_set;
212
wire        cov0_set;
213
 
214
always @ (posedge mclk or posedge puc)
215
  if (puc)             tacctl0  <=  16'h0000;
216
  else if (tacctl0_wr) tacctl0  <=  ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
217
  else                 tacctl0  <=  (tacctl0              | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
218
 
219
wire        cci0;
220
reg         scci0;
221
wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0, 3'h0};
222
 
223
 
224
// TACCR0 Register
225
//------------------   
226
reg  [15:0] taccr0;
227
 
228
wire        taccr0_wr = reg_wr[TACCR0];
229
wire        cci0_cap;
230
 
231
always @ (posedge mclk or posedge puc)
232
  if (puc)            taccr0 <=  16'h0000;
233
  else if (taccr0_wr) taccr0 <=  per_din;
234
  else if (cci0_cap)  taccr0 <=  tar;
235
 
236
 
237
// TACCTL1 Register
238
//------------------   
239
reg  [15:0] tacctl1;
240
 
241
wire        tacctl1_wr = reg_wr[TACCTL1];
242
wire        ccifg1_set;
243
wire        ccifg1_clr;
244
wire        cov1_set;
245
 
246
always @ (posedge mclk or posedge puc)
247
  if (puc)             tacctl1 <=  16'h0000;
248
  else if (tacctl1_wr) tacctl1 <=  ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
249
  else                 tacctl1 <=  (tacctl1              | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
250
 
251
wire        cci1;
252
reg         scci1;
253
wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1, 3'h0};
254
 
255
 
256
// TACCR1 Register
257
//------------------   
258
reg  [15:0] taccr1;
259
 
260
wire        taccr1_wr = reg_wr[TACCR1];
261
wire        cci1_cap;
262
 
263
always @ (posedge mclk or posedge puc)
264
  if (puc)            taccr1 <=  16'h0000;
265
  else if (taccr1_wr) taccr1 <=  per_din;
266
  else if (cci1_cap)  taccr1 <=  tar;
267
 
268
 
269
// TACCTL2 Register
270
//------------------   
271
reg  [15:0] tacctl2;
272
 
273
wire        tacctl2_wr = reg_wr[TACCTL2];
274
wire        ccifg2_set;
275
wire        ccifg2_clr;
276
wire        cov2_set;
277
 
278
always @ (posedge mclk or posedge puc)
279
  if (puc)             tacctl2 <=  16'h0000;
280
  else if (tacctl2_wr) tacctl2 <=  ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
281
  else                 tacctl2 <=  (tacctl2              | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
282
 
283
wire        cci2;
284
reg         scci2;
285
wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2, 3'h0};
286
 
287
 
288
// TACCR2 Register
289
//------------------   
290
reg  [15:0] taccr2;
291
 
292
wire        taccr2_wr = reg_wr[TACCR2];
293
wire        cci2_cap;
294
 
295
always @ (posedge mclk or posedge puc)
296
  if (puc)            taccr2 <=  16'h0000;
297
  else if (taccr2_wr) taccr2 <=  per_din;
298
  else if (cci2_cap)  taccr2 <=  tar;
299
 
300
 
301
// TAIV Register
302
//------------------   
303
 
304
wire [3:0] taiv = (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) ? 4'h2 :
305
                  (tacctl2[`TACCIFG] & tacctl2[`TACCIE]) ? 4'h4 :
306
                  (tactl[`TAIFG]     & tactl[`TAIE])     ? 4'hA :
307
                                                           4'h0;
308
 
309
assign     ccifg1_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h2);
310
assign     ccifg2_clr = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'h4);
311
assign     taifg_clr  = (reg_rd[TAIV] | reg_wr[TAIV]) & (taiv==4'hA);
312
 
313
 
314
//============================================================================
315
// 4) DATA OUTPUT GENERATION
316
//============================================================================
317
 
318
// Data output mux
319
wire [15:0] tactl_rd   = {6'h00, tactl}  & {16{reg_rd[TACTL]}};
320
wire [15:0] tar_rd     = tar             & {16{reg_rd[TAR]}};
321
wire [15:0] tacctl0_rd = tacctl0_full    & {16{reg_rd[TACCTL0]}};
322
wire [15:0] taccr0_rd  = taccr0          & {16{reg_rd[TACCR0]}};
323
wire [15:0] tacctl1_rd = tacctl1_full    & {16{reg_rd[TACCTL1]}};
324
wire [15:0] taccr1_rd  = taccr1          & {16{reg_rd[TACCR1]}};
325
wire [15:0] tacctl2_rd = tacctl2_full    & {16{reg_rd[TACCTL2]}};
326
wire [15:0] taccr2_rd  = taccr2          & {16{reg_rd[TACCR2]}};
327
wire [15:0] taiv_rd    = {12'h000, taiv} & {16{reg_rd[TAIV]}};
328
 
329
wire [15:0] per_dout   =  tactl_rd   |
330
                          tar_rd     |
331
                          tacctl0_rd |
332
                          taccr0_rd  |
333
                          tacctl1_rd |
334
                          taccr1_rd  |
335
                          tacctl2_rd |
336
                          taccr2_rd  |
337
                          taiv_rd;
338
 
339
 
340
//============================================================================
341
// 5) Timer A counter control
342
//============================================================================
343
 
344
// Clock input synchronization (TACLK & INCLK)
345
//-----------------------------------------------------------
346
reg  [2:0] taclk_s;
347
 
348
always @ (posedge mclk or posedge puc)
349
  if (puc) taclk_s <=  3'b000;
350
  else     taclk_s <=  {taclk_s[1:0], taclk};
351
 
352
wire taclk_en = taclk_s[1] & ~taclk_s[2];
353
 
354
 
355
reg  [2:0] inclk_s;
356
 
357
always @ (posedge mclk or posedge puc)
358
  if (puc) inclk_s <=  3'b000;
359
  else     inclk_s <=  {inclk_s[1:0], inclk};
360
 
361
wire inclk_en = inclk_s[1] & ~inclk_s[2];
362
 
363
 
364
// Timer clock input mux
365
//-----------------------------------------------------------
366
 
367
wire sel_clk = (tactl[`TASSELx]==2'b00) ? taclk_en :
368
               (tactl[`TASSELx]==2'b01) ?  aclk_en :
369
               (tactl[`TASSELx]==2'b10) ? smclk_en : inclk_en;
370
 
371
 
372
// Generate update pluse for the counter (<=> divided clock)
373
//-----------------------------------------------------------
374
reg [2:0] clk_div;
375
 
376
assign    tar_clk = sel_clk & ((tactl[`TAIDx]==2'b00) ?  1'b1         :
377
                               (tactl[`TAIDx]==2'b01) ?  clk_div[0]   :
378
                               (tactl[`TAIDx]==2'b10) ? &clk_div[1:0] :
379
                                                        &clk_div[2:0]);
380
 
381
always @ (posedge mclk or posedge puc)
382
  if (puc)                                   clk_div <=  3'h0;
383
  else if  (tar_clk | taclr)                 clk_div <=  3'h0;
384
  else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <=  clk_div+3'h1;
385
 
386
 
387
// Time counter control signals
388
//-----------------------------------------------------------
389
 
390
assign  tar_clr   = ((tactl[`TAMCx]==2'b01) & (tar>=taccr0))         |
391
                    ((tactl[`TAMCx]==2'b11) & (taccr0==16'h0000));
392
 
393
assign  tar_inc   =  (tactl[`TAMCx]==2'b01) | (tactl[`TAMCx]==2'b10) |
394
                    ((tactl[`TAMCx]==2'b11) & ~tar_dec);
395
 
396
reg tar_dir;
397
always @ (posedge mclk or posedge puc)
398
  if (puc)                            tar_dir <=  1'b0;
399
  else if (taclr)                     tar_dir <=  1'b0;
400
  else if (tactl[`TAMCx]==2'b11)
401
    begin
402
       if (tar_clk & (tar==16'h0001)) tar_dir <=  1'b0;
403
       else if       (tar>=taccr0)    tar_dir <=  1'b1;
404
    end
405
  else                                tar_dir <=  1'b0;
406
 
407
assign tar_dec = tar_dir | ((tactl[`TAMCx]==2'b11) & (tar>=taccr0));
408
 
409
 
410
//============================================================================
411
// 6) Timer A comparator
412
//============================================================================
413
 
414
wire equ0 = (tar_nxt==taccr0) & (tar!=taccr0);
415
wire equ1 = (tar_nxt==taccr1) & (tar!=taccr1);
416
wire equ2 = (tar_nxt==taccr2) & (tar!=taccr2);
417
 
418
 
419
//============================================================================
420
// 7) Timer A capture logic
421
//============================================================================
422
 
423
// Input selection
424
//------------------
425
assign cci0 = (tacctl0[`TACCISx]==2'b00) ? ta_cci0a :
426
              (tacctl0[`TACCISx]==2'b01) ? ta_cci0b :
427
              (tacctl0[`TACCISx]==2'b10) ?     1'b0 : 1'b1;
428
 
429
assign cci1 = (tacctl1[`TACCISx]==2'b00) ? ta_cci1a :
430
              (tacctl1[`TACCISx]==2'b01) ? ta_cci1b :
431
              (tacctl1[`TACCISx]==2'b10) ?     1'b0 : 1'b1;
432
 
433
assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
434
              (tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
435
              (tacctl2[`TACCISx]==2'b10) ?     1'b0 : 1'b1;
436
 
437
// Register CCIx for synchronization and edge detection
438
reg [2:0] cci_s;
439
always @ (posedge mclk or posedge puc)
440
  if (puc) cci_s <=  3'h0;
441
  else     cci_s <=  {cci2, cci1, cci0};
442
reg [2:0] cci_ss;
443
always @ (posedge mclk or posedge puc)
444
  if (puc) cci_ss <=  3'h0;
445
  else     cci_ss <=  cci_s;
446
reg [2:0] cci_sss;
447
always @ (posedge mclk or posedge puc)
448
  if (puc) cci_sss <=  3'h0;
449
  else     cci_sss <=  cci_ss;
450
 
451
 
452
// Generate SCCIx
453
//------------------
454
 
455
always @ (posedge mclk or posedge puc)
456
  if (puc)                 scci0 <=  1'b0;
457
  else if (tar_clk & equ0) scci0 <=  cci_ss[0];
458
 
459
always @ (posedge mclk or posedge puc)
460
  if (puc)                 scci1 <=  1'b0;
461
  else if (tar_clk & equ1) scci1 <=  cci_ss[1];
462
 
463
always @ (posedge mclk or posedge puc)
464
  if (puc)                 scci2 <=  1'b0;
465
  else if (tar_clk & equ2) scci2 <=  cci_ss[2];
466
 
467
 
468
// Capture mode
469
//------------------
470
wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0                  :
471
                (tacctl0[`TACMx]==2'b01) ? ( cci_ss[0] & ~cci_sss[0]) :   // Rising edge
472
                (tacctl0[`TACMx]==2'b10) ? (~cci_ss[0] &  cci_sss[0]) :   // Falling edge
473
                                           ( cci_ss[0] ^  cci_sss[0]);    // Both edges
474
 
475
wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0                  :
476
                (tacctl1[`TACMx]==2'b01) ? ( cci_ss[1] & ~cci_sss[1]) :   // Rising edge
477
                (tacctl1[`TACMx]==2'b10) ? (~cci_ss[1] &  cci_sss[1]) :   // Falling edge
478
                                           ( cci_ss[1] ^  cci_sss[1]);    // Both edges
479
 
480
wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0                  :
481
                (tacctl2[`TACMx]==2'b01) ? ( cci_ss[2] & ~cci_sss[2]) :   // Rising edge
482
                (tacctl2[`TACMx]==2'b10) ? (~cci_ss[2] &  cci_sss[2]) :   // Falling edge
483
                                           ( cci_ss[2] ^  cci_sss[2]);    // Both edges
484
 
485
// Event Synchronization
486
//-----------------------
487
 
488
reg cci0_evt_s;
489
always @ (posedge mclk or posedge puc)
490
  if (puc)           cci0_evt_s <=  1'b0;
491
  else if (tar_clk)  cci0_evt_s <=  1'b0;
492
  else if (cci0_evt) cci0_evt_s <=  1'b1;
493
 
494
reg cci1_evt_s;
495
always @ (posedge mclk or posedge puc)
496
  if (puc)           cci1_evt_s <=  1'b0;
497
  else if (tar_clk)  cci1_evt_s <=  1'b0;
498
  else if (cci1_evt) cci1_evt_s <=  1'b1;
499
 
500
reg cci2_evt_s;
501
always @ (posedge mclk or posedge puc)
502
  if (puc)           cci2_evt_s <=  1'b0;
503
  else if (tar_clk)  cci2_evt_s <=  1'b0;
504
  else if (cci2_evt) cci2_evt_s <=  1'b1;
505
 
506
reg cci0_sync;
507
always @ (posedge mclk or posedge puc)
508
  if (puc) cci0_sync <=  1'b0;
509
  else     cci0_sync <=  (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s);
510
 
511
reg cci1_sync;
512
always @ (posedge mclk or posedge puc)
513
  if (puc) cci1_sync <=  1'b0;
514
  else     cci1_sync <=  (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s);
515
 
516
reg cci2_sync;
517
always @ (posedge mclk or posedge puc)
518
  if (puc) cci2_sync <=  1'b0;
519
  else     cci2_sync <=  (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s);
520
 
521
 
522
// Generate final capture command
523
//-----------------------------------
524
 
525
assign cci0_cap  = tacctl0[`TASCS] ? cci0_sync : cci0_evt;
526
assign cci1_cap  = tacctl1[`TASCS] ? cci1_sync : cci1_evt;
527
assign cci2_cap  = tacctl2[`TASCS] ? cci2_sync : cci2_evt;
528
 
529
 
530
// Generate capture overflow flag
531
//-----------------------------------
532
 
533
reg  cap0_taken;
534
wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]);
535
always @ (posedge mclk or posedge puc)
536
  if (puc)                 cap0_taken <=  1'b0;
537
  else if (cci0_cap)       cap0_taken <=  1'b1;
538
  else if (cap0_taken_clr) cap0_taken <=  1'b0;
539
 
540
reg  cap1_taken;
541
wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]);
542
always @ (posedge mclk or posedge puc)
543
  if (puc)                 cap1_taken <=  1'b0;
544
  else if (cci1_cap)       cap1_taken <=  1'b1;
545
  else if (cap1_taken_clr) cap1_taken <=  1'b0;
546
 
547
reg  cap2_taken;
548
wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]);
549
always @ (posedge mclk or posedge puc)
550
  if (puc)                 cap2_taken <=  1'b0;
551
  else if (cci2_cap)       cap2_taken <=  1'b1;
552
  else if (cap2_taken_clr) cap2_taken <=  1'b0;
553
 
554
 
555
assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0];
556
assign cov1_set = cap1_taken & cci1_cap & ~reg_rd[TACCR1];
557
assign cov2_set = cap2_taken & cci2_cap & ~reg_rd[TACCR2];
558
 
559
 
560
//============================================================================
561
// 8) Timer A output unit
562
//============================================================================
563
 
564
// Output unit 0
565
//-------------------
566
reg  ta_out0;
567
 
568
wire ta_out0_mode0 = tacctl0[`TAOUT];                // Output
569
wire ta_out0_mode1 = equ0 ?  1'b1    : ta_out0;      // Set
570
wire ta_out0_mode2 = equ0 ? ~ta_out0 :               // Toggle/Reset
571
                     equ0 ?  1'b0    : ta_out0;
572
wire ta_out0_mode3 = equ0 ?  1'b1    :               // Set/Reset
573
                     equ0 ?  1'b0    : ta_out0;
574
wire ta_out0_mode4 = equ0 ? ~ta_out0 : ta_out0;      // Toggle
575
wire ta_out0_mode5 = equ0 ?  1'b0    : ta_out0;      // Reset
576
wire ta_out0_mode6 = equ0 ? ~ta_out0 :               // Toggle/Set
577
                     equ0 ?  1'b1    : ta_out0;
578
wire ta_out0_mode7 = equ0 ?  1'b0    :               // Reset/Set
579
                     equ0 ?  1'b1    : ta_out0;
580
 
581
wire ta_out0_nxt   = (tacctl0[`TAOUTMODx]==3'b000) ? ta_out0_mode0 :
582
                     (tacctl0[`TAOUTMODx]==3'b001) ? ta_out0_mode1 :
583
                     (tacctl0[`TAOUTMODx]==3'b010) ? ta_out0_mode2 :
584
                     (tacctl0[`TAOUTMODx]==3'b011) ? ta_out0_mode3 :
585
                     (tacctl0[`TAOUTMODx]==3'b100) ? ta_out0_mode4 :
586
                     (tacctl0[`TAOUTMODx]==3'b101) ? ta_out0_mode5 :
587
                     (tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 :
588
                                                     ta_out0_mode7;
589
 
590
always @ (posedge mclk or posedge puc)
591
  if (puc)                                         ta_out0 <=  1'b0;
592
  else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr)  ta_out0 <=  1'b0;
593
  else if (tar_clk)                                ta_out0 <=  ta_out0_nxt;
594
 
595
assign  ta_out0_en = ~tacctl0[`TACAP];
596
 
597
 
598
// Output unit 1
599
//-------------------
600
reg  ta_out1;
601
 
602
wire ta_out1_mode0 = tacctl1[`TAOUT];                // Output
603
wire ta_out1_mode1 = equ1 ?  1'b1    : ta_out1;      // Set
604
wire ta_out1_mode2 = equ1 ? ~ta_out1 :               // Toggle/Reset
605
                     equ0 ?  1'b0    : ta_out1;
606
wire ta_out1_mode3 = equ1 ?  1'b1    :               // Set/Reset
607
                     equ0 ?  1'b0    : ta_out1;
608
wire ta_out1_mode4 = equ1 ? ~ta_out1 : ta_out1;      // Toggle
609
wire ta_out1_mode5 = equ1 ?  1'b0    : ta_out1;      // Reset
610
wire ta_out1_mode6 = equ1 ? ~ta_out1 :               // Toggle/Set
611
                     equ0 ?  1'b1    : ta_out1;
612
wire ta_out1_mode7 = equ1 ?  1'b0    :               // Reset/Set
613
                     equ0 ?  1'b1    : ta_out1;
614
 
615
wire ta_out1_nxt   = (tacctl1[`TAOUTMODx]==3'b000) ? ta_out1_mode0 :
616
                     (tacctl1[`TAOUTMODx]==3'b001) ? ta_out1_mode1 :
617
                     (tacctl1[`TAOUTMODx]==3'b010) ? ta_out1_mode2 :
618
                     (tacctl1[`TAOUTMODx]==3'b011) ? ta_out1_mode3 :
619
                     (tacctl1[`TAOUTMODx]==3'b100) ? ta_out1_mode4 :
620
                     (tacctl1[`TAOUTMODx]==3'b101) ? ta_out1_mode5 :
621
                     (tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 :
622
                                                     ta_out1_mode7;
623
 
624
always @ (posedge mclk or posedge puc)
625
  if (puc)                                         ta_out1 <=  1'b0;
626
  else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr)  ta_out1 <=  1'b0;
627
  else if (tar_clk)                                ta_out1 <=  ta_out1_nxt;
628
 
629
assign  ta_out1_en = ~tacctl1[`TACAP];
630
 
631
 
632
// Output unit 2
633
//-------------------
634
reg  ta_out2;
635
 
636
wire ta_out2_mode0 = tacctl2[`TAOUT];                // Output
637
wire ta_out2_mode1 = equ2 ?  1'b1    : ta_out2;      // Set
638
wire ta_out2_mode2 = equ2 ? ~ta_out2 :               // Toggle/Reset
639
                     equ0 ?  1'b0    : ta_out2;
640
wire ta_out2_mode3 = equ2 ?  1'b1    :               // Set/Reset
641
                     equ0 ?  1'b0    : ta_out2;
642
wire ta_out2_mode4 = equ2 ? ~ta_out2 : ta_out2;      // Toggle
643
wire ta_out2_mode5 = equ2 ?  1'b0    : ta_out2;      // Reset
644
wire ta_out2_mode6 = equ2 ? ~ta_out2 :               // Toggle/Set
645
                     equ0 ?  1'b1    : ta_out2;
646
wire ta_out2_mode7 = equ2 ?  1'b0    :               // Reset/Set
647
                     equ0 ?  1'b1    : ta_out2;
648
 
649
wire ta_out2_nxt   = (tacctl2[`TAOUTMODx]==3'b000) ? ta_out2_mode0 :
650
                     (tacctl2[`TAOUTMODx]==3'b001) ? ta_out2_mode1 :
651
                     (tacctl2[`TAOUTMODx]==3'b010) ? ta_out2_mode2 :
652
                     (tacctl2[`TAOUTMODx]==3'b011) ? ta_out2_mode3 :
653
                     (tacctl2[`TAOUTMODx]==3'b100) ? ta_out2_mode4 :
654
                     (tacctl2[`TAOUTMODx]==3'b101) ? ta_out2_mode5 :
655
                     (tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 :
656
                                                     ta_out2_mode7;
657
 
658
always @ (posedge mclk or posedge puc)
659
  if (puc)                                         ta_out2 <=  1'b0;
660
  else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr)  ta_out2 <=  1'b0;
661
  else if (tar_clk)                                ta_out2 <=  ta_out2_nxt;
662
 
663
assign  ta_out2_en = ~tacctl2[`TACAP];
664
 
665
 
666
//============================================================================
667
// 9) Timer A interrupt generation
668
//============================================================================
669
 
670
 
671
assign   taifg_set   = tar_clk & (((tactl[`TAMCx]==2'b01) & (tar==taccr0))                  |
672
                                  ((tactl[`TAMCx]==2'b10) & (tar==16'hffff))                |
673
                                  ((tactl[`TAMCx]==2'b11) & (tar_nxt==16'h0000) & tar_dec));
674
 
675
assign   ccifg0_set  = tacctl0[`TACAP] ? cci0_cap : (tar_clk &  ((tactl[`TAMCx]!=2'b00) & equ0));
676
assign   ccifg1_set  = tacctl1[`TACAP] ? cci1_cap : (tar_clk &  ((tactl[`TAMCx]!=2'b00) & equ1));
677
assign   ccifg2_set  = tacctl2[`TACAP] ? cci2_cap : (tar_clk &  ((tactl[`TAMCx]!=2'b00) & equ2));
678
 
679
 
680
wire     irq_ta0    = (tacctl0[`TACCIFG] & tacctl0[`TACCIE]);
681
 
682
wire     irq_ta1    = (tactl[`TAIFG]     & tactl[`TAIE])     |
683
                      (tacctl1[`TACCIFG] & tacctl1[`TACCIE]) |
684
                      (tacctl2[`TACCIFG] & tacctl2[`TACCIE]);
685
 
686
 
687 34 olivier.gi
endmodule // omsp_timerA
688 2 olivier.gi
 
689 33 olivier.gi
`include "openMSP430_undefines.v"

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