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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [periph/] [template_periph_16b.v] - Blame information for rev 56

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1 2 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: template_periph_16b.v
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// 
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// *Module Description:
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//                       16 bit peripheral template.
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
34 17 olivier.gi
// $Rev: 33 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
38 23 olivier.gi
`include "timescale.v"
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`include "openMSP430_defines.v"
40 2 olivier.gi
 
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module  template_periph_16b (
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// OUTPUTs
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    per_dout,                       // Peripheral data output
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// INPUTs
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    mclk,                           // Main system clock
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    per_addr,                       // Peripheral address
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    per_din,                        // Peripheral data input
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    per_en,                         // Peripheral enable (high active)
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    per_wen,                        // Peripheral write enable (high active)
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    puc                             // Main system reset
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);
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// OUTPUTs
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//=========
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output       [15:0] per_dout;       // Peripheral data output
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// INPUTs
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//=========
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input               mclk;           // Main system clock
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input         [7:0] per_addr;       // Peripheral address
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input        [15:0] per_din;        // Peripheral data input
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input               per_en;         // Peripheral enable (high active)
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input         [1:0] per_wen;        // Peripheral write enable (high active)
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input               puc;            // Main system reset
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//=============================================================================
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// 1)  PARAMETER DECLARATION
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//=============================================================================
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// Register addresses
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parameter           CNTRL1     = 9'h190;
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parameter           CNTRL2     = 9'h192;
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parameter           CNTRL3     = 9'h194;
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parameter           CNTRL4     = 9'h196;
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// Register one-hot decoder
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parameter           CNTRL1_D   = (512'h1 << CNTRL1);
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parameter           CNTRL2_D   = (512'h1 << CNTRL2);
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parameter           CNTRL3_D   = (512'h1 << CNTRL3);
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parameter           CNTRL4_D   = (512'h1 << CNTRL4);
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//============================================================================
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// 2)  REGISTER DECODER
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//============================================================================
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// Register address decode
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reg  [511:0]  reg_dec;
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always @(per_addr)
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  case ({per_addr,1'b0})
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    CNTRL1 :     reg_dec  =  CNTRL1_D;
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    CNTRL2 :     reg_dec  =  CNTRL2_D;
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    CNTRL3 :     reg_dec  =  CNTRL3_D;
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    CNTRL4 :     reg_dec  =  CNTRL4_D;
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    default:     reg_dec  =  {512{1'b0}};
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  endcase
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// Read/Write probes
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wire         reg_write =  |per_wen   & per_en;
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wire         reg_read  = ~|per_wen   & per_en;
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// Read/Write vectors
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wire [511:0] reg_wr    = reg_dec & {512{reg_write}};
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wire [511:0] reg_rd    = reg_dec & {512{reg_read}};
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//============================================================================
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// 3) REGISTERS
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//============================================================================
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// CNTRL1 Register
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//-----------------   
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reg  [15:0] cntrl1;
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wire        cntrl1_wr = reg_wr[CNTRL1];
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always @ (posedge mclk or posedge puc)
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  if (puc)            cntrl1 <=  16'h0000;
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  else if (cntrl1_wr) cntrl1 <=  per_din;
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// CNTRL2 Register
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//-----------------   
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reg  [15:0] cntrl2;
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wire        cntrl2_wr = reg_wr[CNTRL2];
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always @ (posedge mclk or posedge puc)
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  if (puc)            cntrl2 <=  16'h0000;
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  else if (cntrl2_wr) cntrl2 <=  per_din;
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// CNTRL3 Register
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//-----------------   
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reg  [15:0] cntrl3;
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wire        cntrl3_wr = reg_wr[CNTRL3];
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always @ (posedge mclk or posedge puc)
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  if (puc)            cntrl3 <=  16'h0000;
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  else if (cntrl3_wr) cntrl3 <=  per_din;
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// CNTRL4 Register
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//-----------------   
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reg  [15:0] cntrl4;
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wire        cntrl4_wr = reg_wr[CNTRL4];
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always @ (posedge mclk or posedge puc)
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  if (puc)            cntrl4 <=  16'h0000;
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  else if (cntrl4_wr) cntrl4 <=  per_din;
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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// Data output mux
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wire [15:0] cntrl1_rd  = cntrl1  & {16{reg_rd[CNTRL1]}};
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wire [15:0] cntrl2_rd  = cntrl2  & {16{reg_rd[CNTRL2]}};
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wire [15:0] cntrl3_rd  = cntrl3  & {16{reg_rd[CNTRL3]}};
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wire [15:0] cntrl4_rd  = cntrl4  & {16{reg_rd[CNTRL4]}};
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wire [15:0] per_dout   =  cntrl1_rd  |
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                          cntrl2_rd  |
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                          cntrl3_rd  |
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                          cntrl4_rd;
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endmodule // template_periph_16b
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177 33 olivier.gi
`include "openMSP430_undefines.v"

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