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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] [hw_uart.v] - Blame information for rev 136

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/*===========================================================================*/
/*                                 DIGITAL I/O                               */
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface.                                           */
/*===========================================================================*/
 
reg [32*8-1:0] rx_chain;
integer        rx_offset;
 
 
reg [7:0] rxbuf;
integer   rxcnt;
`define   BAUD    140
 
task uart_rx;
      begin
         @(negedge UART_TXD);
         rxbuf = 0;
         repeat(`BAUD*3/2) @(posedge mclk);
         for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
           begin
              rxbuf = {UART_TXD, rxbuf[7:1]};
              repeat(`BAUD) @(posedge mclk);
        end
      end
endtask
 
task uart_tx;
      input [7:0] txbuf;
 
      reg [9:0] txbuf_full;
      integer   txcnt;
      begin
         UART_RXD = 1'b1;
         txbuf_full = {1'b1, txbuf, 1'b0};
         repeat(`BAUD) @(posedge mclk);
         for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
           begin
              UART_RXD   =  txbuf_full[txcnt];
//            txbuf_full = {txbuf_full[8:1], 1'b0};
              repeat(`BAUD) @(posedge mclk);
           end
      end
endtask
 
 
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      repeat(5) @(posedge CLK_50MHz);
      stimulus_done = 0;
      rx_chain = 0;
      rx_offset = 0;
 
      while (rx_offset<1)
        begin
           uart_rx;
           rx_chain = rx_chain | (rxbuf << (31*8-(8*rx_offset)));
           rx_offset = rx_offset+1;
        end
 
      repeat(50) @(posedge CLK_50MHz);
      uart_tx("a");
 
//      repeat(5000) @(posedge mclk);
//      UART_RXD = 1;
//      repeat(160) @(posedge mclk);
//      UART_RXD = 0;
//      repeat(160) @(posedge mclk);
//      UART_RXD = 1;
//      repeat(160) @(posedge mclk);
//      UART_RXD = 0;
//      repeat(160) @(posedge mclk);
//      UART_RXD = 1;
//      repeat(160) @(posedge mclk);
//      UART_RXD = 0;
//      repeat(160) @(posedge mclk);
//      UART_RXD = 1;
//      repeat(160) @(posedge mclk);
//      UART_RXD = 0;
//      repeat(160) @(posedge mclk);
 
 
      stimulus_done = 1;
      //repeat(1000) @(posedge mclk);
      //$finish();
 
   end
 

Line No.	Rev	Author	Line
1	136	olivier.gi	`/===========================================================================/`
2			`/* DIGITAL I/O */`
3			`/---------------------------------------------------------------------------/`
4			`/* Test the Digital I/O interface. */`
5			`/===========================================================================/`
6
7			`reg [32*8-1:0] rx_chain;`
8			`integer rx_offset;`
9
10
11			`reg [7:0] rxbuf;`
12			`integer rxcnt;`
13			`define BAUD 140
14
15			`task uart_rx;`
16			`begin`
17			`@(negedge UART_TXD);`
18			`rxbuf = 0;`
19			repeat(`BAUD*3/2) @(posedge mclk);
20			`for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)`
21			`begin`
22			`rxbuf = {UART_TXD, rxbuf[7:1]};`
23			repeat(`BAUD) @(posedge mclk);
24			`end`
25			`end`
26			`endtask`
27
28			`task uart_tx;`
29			`input [7:0] txbuf;`
30
31			`reg [9:0] txbuf_full;`
32			`integer txcnt;`
33			`begin`
34			`UART_RXD = 1'b1;`
35			`txbuf_full = {1'b1, txbuf, 1'b0};`
36			repeat(`BAUD) @(posedge mclk);
37			`for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)`
38			`begin`
39			`UART_RXD = txbuf_full[txcnt];`
40			`// txbuf_full = {txbuf_full[8:1], 1'b0};`
41			repeat(`BAUD) @(posedge mclk);
42			`end`
43			`end`
44			`endtask`
45
46
47
48			`initial`
49			`begin`
50			`$display(" ===============================================");`
51			`$display("\| START SIMULATION \|");`
52			`$display(" ===============================================");`
53			`repeat(5) @(posedge CLK_50MHz);`
54			`stimulus_done = 0;`
55			`rx_chain = 0;`
56			`rx_offset = 0;`
57
58			`while (rx_offset<1)`
59			`begin`
60			`uart_rx;`
61			`rx_chain = rx_chain \| (rxbuf << (318-(8rx_offset)));`
62			`rx_offset = rx_offset+1;`
63			`end`
64
65			`repeat(50) @(posedge CLK_50MHz);`
66			`uart_tx("a");`
67
68			`// repeat(5000) @(posedge mclk);`
69			`// UART_RXD = 1;`
70			`// repeat(160) @(posedge mclk);`
71			`// UART_RXD = 0;`
72			`// repeat(160) @(posedge mclk);`
73			`// UART_RXD = 1;`
74			`// repeat(160) @(posedge mclk);`
75			`// UART_RXD = 0;`
76			`// repeat(160) @(posedge mclk);`
77			`// UART_RXD = 1;`
78			`// repeat(160) @(posedge mclk);`
79			`// UART_RXD = 0;`
80			`// repeat(160) @(posedge mclk);`
81			`// UART_RXD = 1;`
82			`// repeat(160) @(posedge mclk);`
83			`// UART_RXD = 0;`
84			`// repeat(160) @(posedge mclk);`
85
86
87			`stimulus_done = 1;`
88			`//repeat(1000) @(posedge mclk);`
89			`//$finish();`
90
91			`end`
92

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] [hw_uart.v] - Blame information for rev 136