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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] [leds.v] - Blame information for rev 98

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Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
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/*                                 DIGITAL I/O                               */
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/*---------------------------------------------------------------------------*/
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/* Test the Digital I/O interface.                                           */
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/*===========================================================================*/
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge CLK_50MHz);
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      stimulus_done = 0;
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      stimulus_done = 1;
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   end
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