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olivier.gi |
//=============================================================================
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// Xilinx library
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//=============================================================================
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+libext+.v
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-y /opt/Xilinx/10.1/ISE/verilog/src/unisims/
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-y /opt/Xilinx/10.1/ISE/verilog/src/simprims/
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-y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib/
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//=============================================================================
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// FPGA Specific modules
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//=============================================================================
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+incdir+../../../rtl/verilog/
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../../../rtl/verilog/openMSP430.inc
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../../../rtl/verilog/openMSP430_fpga.v
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../../../rtl/verilog/io_mux.v
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../../../rtl/verilog/driver_7segment.v
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../../../rtl/verilog/coregen/ram_8x512_hi.v
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../../../rtl/verilog/coregen/ram_8x512_lo.v
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../../../rtl/verilog/coregen/rom_8x2k_hi.v
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../../../rtl/verilog/coregen/rom_8x2k_lo.v
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//=============================================================================
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// openMSP430
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//=============================================================================
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../../../../../core/rtl/verilog/openMSP430.v
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../../../../../core/rtl/verilog/frontend.v
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../../../../../core/rtl/verilog/execution_unit.v
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../../../../../core/rtl/verilog/register_file.v
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../../../../../core/rtl/verilog/alu.v
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../../../../../core/rtl/verilog/mem_backbone.v
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../../../../../core/rtl/verilog/clock_module.v
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../../../../../core/rtl/verilog/sfr.v
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../../../../../core/rtl/verilog/dbg.v
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../../../../../core/rtl/verilog/dbg_hwbrk.v
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../../../../../core/rtl/verilog/dbg_uart.v
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../../../../../core/rtl/verilog/watchdog.v
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../../../../../core/rtl/verilog/periph/gpio.v
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../../../../../core/rtl/verilog/periph/timerA.v
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//=============================================================================
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// Testbench related
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//=============================================================================
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+incdir+../../../bench/verilog/
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../../../bench/verilog/tb_openMSP430_fpga.v
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../../../bench/verilog/msp_debug.v
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../../../bench/verilog/glbl.v
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