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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [hw_uart/] [hardware.h] - Blame information for rev 136

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#ifndef HARDWARE_H
#define HARDWARE_H
 
#define __msp430_have_port3
#define __MSP430_HAS_PORT3__
 
#include <io.h>
#include <signal.h>
#include <iomacros.h>
 
//--------------------------------------------------
// Hardware UART register address mapping
//--------------------------------------------------
 
#define UART_CTL_           0x0080  // UART Control register (8bit)
sfrb(UART_CTL,UART_CTL_);
 
#define UART_STAT_          0x0081  // UART Status register (8bit)
sfrb(UART_STAT,UART_STAT_);
 
#define UART_BAUD_          0x0082  // UART Baud rate configuration (16bit)
sfrw(UART_BAUD,UART_BAUD_);
 
#define UART_TXD_           0x0084  // UART Transmit data register (8bit)
sfrb(UART_TXD,UART_TXD_);
 
#define UART_RXD_           0x0085  // UART Receive data register (8bit)
sfrb(UART_RXD,UART_RXD_);
 
 
//--------------------------------------------------
// Hardware UART register field mapping
//--------------------------------------------------
 
// UART Control register fields
#define  UART_IEN_TX_EMPTY  0x80
#define  UART_IEN_TX        0x40
#define  UART_IEN_RX_OVFLW  0x20
#define  UART_IEN_RX        0x10
#define  UART_SMCLK_SEL     0x02
#define  UART_EN            0x01
 
// UART Status register fields
#define  UART_TX_EMPTY_PND  0x80
#define  UART_TX_PND        0x40
#define  UART_RX_OVFLW_PND  0x20
#define  UART_RX_PND        0x10
#define  UART_TX_FULL       0x08
#define  UART_TX_BUSY       0x04
#define  UART_RX_BUSY       0x01
 
 
//--------------------------------------------------
// Hardware UART interrupt mapping
//--------------------------------------------------
 
#define UART_TX_VECTOR      (6 *2) // Interrupt vector 6  (0xFFEC)
#define UART_RX_VECTOR      (7 *2) // Interrupt vector 7  (0xFFEE)
 
 
//--------------------------------------------------
// Diverse
//--------------------------------------------------
 
// BAUD = (mclk_freq/baudrate)-1
 
//#define BAUD           2083            //   9600  @20.0MHz
//#define BAUD           1042            //  19200  @20.0MHz
//#define BAUD            521            //  38400  @20.0MHz
//#define BAUD            347            //  57600  @20.0MHz
#define BAUD            174            // 115200  @20.0MHz
//#define BAUD             87            // 230400  @20.0MHz
 
 
 
 
#endif //HARDWARE_H

Line No.	Rev	Author	Line
1	136	olivier.gi	`#ifndef HARDWARE_H`
2			`#define HARDWARE_H`
3
4			`#define __msp430_have_port3`
5			`#define __MSP430_HAS_PORT3__`
6
7			`#include <io.h>`
8			`#include <signal.h>`
9			`#include <iomacros.h>`
10
11			`//--------------------------------------------------`
12			`// Hardware UART register address mapping`
13			`//--------------------------------------------------`
14
15			`#define UART_CTL_ 0x0080 // UART Control register (8bit)`
16			`sfrb(UART_CTL,UART_CTL_);`
17
18			`#define UART_STAT_ 0x0081 // UART Status register (8bit)`
19			`sfrb(UART_STAT,UART_STAT_);`
20
21			`#define UART_BAUD_ 0x0082 // UART Baud rate configuration (16bit)`
22			`sfrw(UART_BAUD,UART_BAUD_);`
23
24			`#define UART_TXD_ 0x0084 // UART Transmit data register (8bit)`
25			`sfrb(UART_TXD,UART_TXD_);`
26
27			`#define UART_RXD_ 0x0085 // UART Receive data register (8bit)`
28			`sfrb(UART_RXD,UART_RXD_);`
29
30
31			`//--------------------------------------------------`
32			`// Hardware UART register field mapping`
33			`//--------------------------------------------------`
34
35			`// UART Control register fields`
36			`#define UART_IEN_TX_EMPTY 0x80`
37			`#define UART_IEN_TX 0x40`
38			`#define UART_IEN_RX_OVFLW 0x20`
39			`#define UART_IEN_RX 0x10`
40			`#define UART_SMCLK_SEL 0x02`
41			`#define UART_EN 0x01`
42
43			`// UART Status register fields`
44			`#define UART_TX_EMPTY_PND 0x80`
45			`#define UART_TX_PND 0x40`
46			`#define UART_RX_OVFLW_PND 0x20`
47			`#define UART_RX_PND 0x10`
48			`#define UART_TX_FULL 0x08`
49			`#define UART_TX_BUSY 0x04`
50			`#define UART_RX_BUSY 0x01`
51
52
53			`//--------------------------------------------------`
54			`// Hardware UART interrupt mapping`
55			`//--------------------------------------------------`
56
57			`#define UART_TX_VECTOR (6 *2) // Interrupt vector 6 (0xFFEC)`
58			`#define UART_RX_VECTOR (7 *2) // Interrupt vector 7 (0xFFEE)`
59
60
61			`//--------------------------------------------------`
62			`// Diverse`
63			`//--------------------------------------------------`
64
65			`// BAUD = (mclk_freq/baudrate)-1`
66
67			`//#define BAUD 2083 // 9600 @20.0MHz`
68			`//#define BAUD 1042 // 19200 @20.0MHz`
69			`//#define BAUD 521 // 38400 @20.0MHz`
70			`//#define BAUD 347 // 57600 @20.0MHz`
71			`#define BAUD 174 // 115200 @20.0MHz`
72			`//#define BAUD 87 // 230400 @20.0MHz`
73
74
75
76
77			`#endif //HARDWARE_H`

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [hw_uart/] [hardware.h] - Blame information for rev 136