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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [hw_uart/] [hardware.h] - Blame information for rev 143

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#ifndef HARDWARE_H
#define HARDWARE_H
 
 
//--------------------------------------------------
// Hardware UART register address mapping
//--------------------------------------------------
 
#define UART_CTL          (*(volatile unsigned char *) 0x0080)  // UART Control register (8bit)
#define UART_STAT         (*(volatile unsigned char *) 0x0081)  // UART Status register (8bit)
#define UART_BAUD         (*(volatile unsigned int  *) 0x0082)  // UART Baud rate configuration (16bit)
#define UART_TXD          (*(volatile unsigned char *) 0x0084)  // UART Transmit data register (8bit)
#define UART_RXD          (*(volatile unsigned char *) 0x0085)  // UART Receive data register (8bit)
 
 
//--------------------------------------------------
// Hardware UART register field mapping
//--------------------------------------------------
 
// UART Control register fields
#define  UART_IEN_TX_EMPTY  0x80
#define  UART_IEN_TX        0x40
#define  UART_IEN_RX_OVFLW  0x20
#define  UART_IEN_RX        0x10
#define  UART_SMCLK_SEL     0x02
#define  UART_EN            0x01
 
// UART Status register fields
#define  UART_TX_EMPTY_PND  0x80
#define  UART_TX_PND        0x40
#define  UART_RX_OVFLW_PND  0x20
#define  UART_RX_PND        0x10
#define  UART_TX_FULL       0x08
#define  UART_TX_BUSY       0x04
#define  UART_RX_BUSY       0x01
 
 
//--------------------------------------------------
// Hardware UART interrupt mapping
//--------------------------------------------------
 
#define UART_TX_VECTOR      (6 *2) // Interrupt vector 6  (0xFFEC)
#define UART_RX_VECTOR      (7 *2) // Interrupt vector 7  (0xFFEE)
 
 
//--------------------------------------------------
// Diverse
//--------------------------------------------------
 
// BAUD = (mclk_freq/baudrate)-1
 
//#define BAUD           2083            //   9600  @20.0MHz
//#define BAUD           1042            //  19200  @20.0MHz
//#define BAUD            521            //  38400  @20.0MHz
//#define BAUD            347            //  57600  @20.0MHz
#define BAUD            174            // 115200  @20.0MHz
//#define BAUD             87            // 230400  @20.0MHz
 
 
 
 
#endif //HARDWARE_H

Line No.	Rev	Author	Line
1	136	olivier.gi	`#ifndef HARDWARE_H`
2			`#define HARDWARE_H`
3
4
5			`//--------------------------------------------------`
6			`// Hardware UART register address mapping`
7			`//--------------------------------------------------`
8
9	143	olivier.gi	`#define UART_CTL ((volatile unsigned char ) 0x0080) // UART Control register (8bit)`
10			`#define UART_STAT ((volatile unsigned char ) 0x0081) // UART Status register (8bit)`
11			`#define UART_BAUD ((volatile unsigned int ) 0x0082) // UART Baud rate configuration (16bit)`
12			`#define UART_TXD ((volatile unsigned char ) 0x0084) // UART Transmit data register (8bit)`
13			`#define UART_RXD ((volatile unsigned char ) 0x0085) // UART Receive data register (8bit)`
14	136	olivier.gi
15
16			`//--------------------------------------------------`
17			`// Hardware UART register field mapping`
18			`//--------------------------------------------------`
19
20			`// UART Control register fields`
21			`#define UART_IEN_TX_EMPTY 0x80`
22			`#define UART_IEN_TX 0x40`
23			`#define UART_IEN_RX_OVFLW 0x20`
24			`#define UART_IEN_RX 0x10`
25			`#define UART_SMCLK_SEL 0x02`
26			`#define UART_EN 0x01`
27
28			`// UART Status register fields`
29			`#define UART_TX_EMPTY_PND 0x80`
30			`#define UART_TX_PND 0x40`
31			`#define UART_RX_OVFLW_PND 0x20`
32			`#define UART_RX_PND 0x10`
33			`#define UART_TX_FULL 0x08`
34			`#define UART_TX_BUSY 0x04`
35			`#define UART_RX_BUSY 0x01`
36
37
38			`//--------------------------------------------------`
39			`// Hardware UART interrupt mapping`
40			`//--------------------------------------------------`
41
42			`#define UART_TX_VECTOR (6 *2) // Interrupt vector 6 (0xFFEC)`
43			`#define UART_RX_VECTOR (7 *2) // Interrupt vector 7 (0xFFEE)`
44
45
46			`//--------------------------------------------------`
47			`// Diverse`
48			`//--------------------------------------------------`
49
50			`// BAUD = (mclk_freq/baudrate)-1`
51
52			`//#define BAUD 2083 // 9600 @20.0MHz`
53			`//#define BAUD 1042 // 19200 @20.0MHz`
54			`//#define BAUD 521 // 38400 @20.0MHz`
55			`//#define BAUD 347 // 57600 @20.0MHz`
56			`#define BAUD 174 // 115200 @20.0MHz`
57			`//#define BAUD 87 // 230400 @20.0MHz`
58
59
60
61
62			`#endif //HARDWARE_H`

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [hw_uart/] [hardware.h] - Blame information for rev 143