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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [hw_uart/] [omsp_uart.h] - Blame information for rev 136

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Line No. Rev Author Line
1 136 olivier.gi
#ifndef OMSP_UART_H
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#define OMSP_UART_H
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#include <io.h>
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#include <signal.h>
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#include <iomacros.h>
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//--------------------------------------------------
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// Hardware UART register address mapping
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//--------------------------------------------------
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#define UART_CTL_           0x0080  // UART Control register (8bit)
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sfrb(UART_CTL,UART_CTL_);
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#define UART_STAT_          0x0081  // UART Status register (8bit)
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sfrb(UART_STAT,UART_STAT_);
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#define UART_BAUD_          0x0082  // UART Baud rate configuration (16bit)
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sfrw(UART_BAUD,UART_BAUD_);
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#define UART_TXD_           0x0084  // UART Transmit data register (8bit)
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sfrb(UART_TXD,UART_TXD_);
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#define UART_RXD_           0x0085  // UART Receive data register (8bit)
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sfrb(UART_RXD,UART_RXD_);
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//--------------------------------------------------
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// Hardware UART register field mapping
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//--------------------------------------------------
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// UART Control register fields
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#define  UART_IEN_TX_EMPTY  0x80
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#define  UART_IEN_TX        0x40
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#define  UART_IEN_RX_OVFLW  0x20
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#define  UART_IEN_RX        0x10
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#define  UART_SMCLK_SEL     0x02
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#define  UART_EN            0x01
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// UART Status register fields
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#define  UART_TX_EMPTY_PND  0x80
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#define  UART_TX_PND        0x40
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#define  UART_RX_OVFLW_PND  0x20
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#define  UART_RX_PND        0x10
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#define  UART_TX_FULL       0x08
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#define  UART_TX_BUSY       0x04
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#define  UART_RX_BUSY       0x01
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//--------------------------------------------------
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// Hardware UART interrupt mapping
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//--------------------------------------------------
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#define UART_TX_VECTOR      (6 *2) // Interrupt vector 6  (0xFFEC)
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#define UART_RX_VECTOR      (7 *2) // Interrupt vector 7  (0xFFEE)
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#endif

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