OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [hw_uart/] [omsp_uart.h] - Blame information for rev 202

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 136 olivier.gi
#ifndef OMSP_UART_H
2
#define OMSP_UART_H
3
 
4
#include <io.h>
5
#include <signal.h>
6
#include <iomacros.h>
7
 
8
//--------------------------------------------------
9
// Hardware UART register address mapping
10
//--------------------------------------------------
11
 
12
#define UART_CTL_           0x0080  // UART Control register (8bit)
13
sfrb(UART_CTL,UART_CTL_);
14
 
15
#define UART_STAT_          0x0081  // UART Status register (8bit)
16
sfrb(UART_STAT,UART_STAT_);
17
 
18
#define UART_BAUD_          0x0082  // UART Baud rate configuration (16bit)
19
sfrw(UART_BAUD,UART_BAUD_);
20
 
21
#define UART_TXD_           0x0084  // UART Transmit data register (8bit)
22
sfrb(UART_TXD,UART_TXD_);
23
 
24
#define UART_RXD_           0x0085  // UART Receive data register (8bit)
25
sfrb(UART_RXD,UART_RXD_);
26
 
27
 
28
//--------------------------------------------------
29
// Hardware UART register field mapping
30
//--------------------------------------------------
31
 
32
// UART Control register fields
33
#define  UART_IEN_TX_EMPTY  0x80
34
#define  UART_IEN_TX        0x40
35
#define  UART_IEN_RX_OVFLW  0x20
36
#define  UART_IEN_RX        0x10
37
#define  UART_SMCLK_SEL     0x02
38
#define  UART_EN            0x01
39
 
40
// UART Status register fields
41
#define  UART_TX_EMPTY_PND  0x80
42
#define  UART_TX_PND        0x40
43
#define  UART_RX_OVFLW_PND  0x20
44
#define  UART_RX_PND        0x10
45
#define  UART_TX_FULL       0x08
46
#define  UART_TX_BUSY       0x04
47
#define  UART_RX_BUSY       0x01
48
 
49
 
50
//--------------------------------------------------
51
// Hardware UART interrupt mapping
52
//--------------------------------------------------
53
 
54
#define UART_TX_VECTOR      (6 *2) // Interrupt vector 6  (0xFFEC)
55
#define UART_RX_VECTOR      (7 *2) // Interrupt vector 7  (0xFFEE)
56
 
57
 
58
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.