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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [ta_uart/] [hardware.h] - Blame information for rev 202

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Line No. Rev Author Line
1 2 olivier.gi
#ifndef HARDWARE_H
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#define HARDWARE_H
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4 143 olivier.gi
#include <msp430.h>
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#include <legacymsp430.h>
6 2 olivier.gi
#include <iomacros.h>
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//PINS
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//PORT1
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#define TX              BIT1
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//PORT2
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#define RX              BIT2
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#define LED             BIT1
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//Port Output Register 'P1OUT, P2OUT':
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#define P1OUT_INIT      TX              //Init Output data of port1
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#define P2OUT_INIT      0               //Init Output data of port2
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#define P3OUT_INIT      0               //Init Output data of port3
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//Port Direction Register 'P1DIR, P2DIR':
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#define P1DIR_INIT      TX              //Init of Port1 Data-Direction Reg (Out=1 / Inp=0)
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#define P2DIR_INIT      ~RX             //Init of Port2 Data-Direction Reg (Out=1 / Inp=0)
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#define P3DIR_INIT      0xff            //Init of Port3 Data-Direction Reg (Out=1 / Inp=0)
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//Selection of Port or Module -Function on the Pins 'P1SEL, P2SEL'
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#define P1SEL_INIT      0               //P1-Modules:
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#define P2SEL_INIT      RX              //P2-Modules:
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#define P3SEL_INIT      0               //P3-Modules:
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//Interrupt capabilities of P1 and P2
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#define P1IE_INIT       0               //Interrupt Enable (0=dis 1=enabled)
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#define P2IE_INIT       0               //Interrupt Enable (0=dis 1=enabled)
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#define P1IES_INIT      0               //Interrupt Edge Select (0=pos 1=neg)
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#define P2IES_INIT      0               //Interrupt Edge Select (0=pos 1=neg)
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#define IE_INIT         0
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#define WDTCTL_INIT     WDTPW|WDTHOLD
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#define BCSCTL1_FLL     XT2OFF|DIVA1|RSEL2|RSEL0
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#define BCSCTL2_FLL     0
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#define TACTL_FLL       TASSEL_2|TACLR
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#define CCTL2_FLL       CM0|CCIS0|CAP
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#define TACTL_AFTER_FLL TASSEL_2|TACLR|ID_0
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//#define BAUD            40              //9600 @3MHz div 8
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//#define BAUD            20              //19200 @3MHz div 8
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//#define BAUD            20              //9600 @1.5MHz div 8
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//#define BAUD            140              //9600 @1.5MHz div 8
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//#define BAUD           2083              //9600 @20.0MHz div 1
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//#define BAUD           1042              //19200 @20.0MHz div 1
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//#define BAUD            521              //38400 @20.0MHz div 1
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//#define BAUD            347              //57600 @20.0MHz div 1
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#define BAUD            174              //115200 @20.0MHz div 1
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//#define BAUD             87              //230400 @20.0MHz div 1
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//Selection of 'Digitally Controlled Oszillator' (desired frquency in HZ, 1..3 MHz)
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#define DCO_FREQ        1536000         //3072000/2 makes 9600 a bit more precise
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//Automatic, do not edit
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#define DCO_FSET        (DCO_FREQ/8192) //DCO_FSET = DCO_FREQ / (32768/4)
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#define DCOCTL_MAX      0xff            // Used from FLL to check when Rsel must be changed
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#define DCOCTL_MIN      0               // Used from FLL to check when Rsel must be changed
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#endif //HARDWARE_H

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