URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [synthesis/] [xilinx/] [win_0_create_bitstream.bat] - Blame information for rev 153

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::######################################################
::#                                                    #
::# Xilinx Synthesis, Place & Route script for WINDOWS #
::#                                                    #
::######################################################
 
:: Cleanup
RMDIR /S /Q .\WORK
MKDIR WORK
cd ./WORK
 
:: Copy the RAM & ROM ngc files
XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_hi.ngc .
XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_lo.ngc .
XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_hi.ngc  .
XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_lo.ngc  .
 
:: Copy the Xilinx constraints file
XCOPY ..\scripts\openMSP430_fpga.ucf                .
 
:: Create link to the TimerA include file
XCOPY ..\..\..\rtl\verilog\openmsp430\periph\omsp_timerA_defines.v    .
XCOPY ..\..\..\rtl\verilog\openmsp430\periph\omsp_timerA_undefines.v  .
 
:: XFLOW
::---------------
 
xflow -p 3S200FT256-4 -implement high_effort.opt            ^
                      -config    bitgen.opt                 ^
                      -synth     ..\scripts\xst_verilog.opt ^
                      ..\scripts\openMSP430_fpga.prj
 
:: MANUAL FLOW
::---------------
 
::xst      -intstyle xflow    -ifn ..\openMSP430_fpga.xst
 
::ngdbuild -p xc3s200-4-ft256 -uc  ..\openMSP430_fpga.ucf openMSP430_fpga
 
::map -k 6 -detail -pr b openMSP430_fpga
 
::par -ol med -w openMSP430_fpga.ncd openMSP430_fpga
 
::trce -e -o openMSP430_fpga_err.twr openMSP430_fpga
::trce -v -o openMSP430_fpga_ver.twr openMSP430_fpga
 
::bitgen -w -g UserID:5555000 -g DonePipe:yes -g UnusedPin:Pullup openMSP430_fpga
 
 
cd ..
 
XCOPY .\WORK\openMSP430_fpga.bit .\bitstreams\.
 
PAUSE

Line No.	Rev	Author	Line
1	25	olivier.gi	`::######################################################`
2			`::# #`
3			`::# Xilinx Synthesis, Place & Route script for WINDOWS #`
4			`::# #`
5			`::######################################################`
6
7			`:: Cleanup`
8			`RMDIR /S /Q .\WORK`
9			`MKDIR WORK`
10			`cd ./WORK`
11
12			`:: Copy the RAM & ROM ngc files`
13			`XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_hi.ngc .`
14			`XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_lo.ngc .`
15			`XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_hi.ngc .`
16			`XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_lo.ngc .`
17
18			`:: Copy the Xilinx constraints file`
19	153	olivier.gi	`XCOPY ..\scripts\openMSP430_fpga.ucf .`
20	25	olivier.gi
21	153	olivier.gi	`:: Create link to the TimerA include file`
22			`XCOPY ..\..\..\rtl\verilog\openmsp430\periph\omsp_timerA_defines.v .`
23			`XCOPY ..\..\..\rtl\verilog\openmsp430\periph\omsp_timerA_undefines.v .`
24	25	olivier.gi
25			`:: XFLOW`
26			`::---------------`
27
28	153	olivier.gi	`xflow -p 3S200FT256-4 -implement high_effort.opt ^`
29			`-config bitgen.opt ^`
30			`-synth ..\scripts\xst_verilog.opt ^`
31			`..\scripts\openMSP430_fpga.prj`
32	25	olivier.gi
33			`:: MANUAL FLOW`
34			`::---------------`
35
36			`::xst -intstyle xflow -ifn ..\openMSP430_fpga.xst`
37
38			`::ngdbuild -p xc3s200-4-ft256 -uc ..\openMSP430_fpga.ucf openMSP430_fpga`
39
40			`::map -k 6 -detail -pr b openMSP430_fpga`
41
42			`::par -ol med -w openMSP430_fpga.ncd openMSP430_fpga`
43
44			`::trce -e -o openMSP430_fpga_err.twr openMSP430_fpga`
45			`::trce -v -o openMSP430_fpga_ver.twr openMSP430_fpga`
46
47			`::bitgen -w -g UserID:5555000 -g DonePipe:yes -g UnusedPin:Pullup openMSP430_fpga`
48
49
50			`cd ..`
51	153	olivier.gi
52			`XCOPY .\WORK\openMSP430_fpga.bit .\bitstreams\.`
53
54	25	olivier.gi	`PAUSE`

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [synthesis/] [xilinx/] [win_0_create_bitstream.bat] - Blame information for rev 153