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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [d10v-elf/] [t-sp.s] - Blame information for rev 33

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Line No. Rev Author Line
1 24 jeremybenn
.include "t-macros.i"
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        start
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;;; Read/Write values to SPU/SPI
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        loadpsw2 0
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        ldi sp, 0xdead
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        loadpsw2 PSW_SM
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        ldi sp, 0xbeef
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        loadpsw2 0
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        check 1 sp 0xdead
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        loadpsw2 PSW_SM
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        check 2 sp 0xbeef
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        exit0

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