URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wzero.cgs] - Blame information for rev 33

Details | Compare with Previous | View Log


# Intel(r) Wireless MMX(tm) technology testcase for WZERO
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global wzero
wzero:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
 
        tmcrr      wr0, r0, r1
 
        wzero      wr0
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0x00000000
        test_h_gr  r1, 0x00000000
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Intel(r) Wireless MMX(tm) technology testcase for WZERO`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global wzero`
10			`wzero:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`mvi_h_gr r0, 0x12345678`
18			`mvi_h_gr r1, 0x9abcdef0`
19
20			`tmcrr wr0, r0, r1`
21
22			`wzero wr0`
23
24			`tmrrc r0, r1, wr0`
25
26			`test_h_gr r0, 0x00000000`
27			`test_h_gr r1, 0x00000000`
28
29			`pass`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wzero.cgs] - Blame information for rev 33