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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [movect10.ms] - Blame information for rev 33

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Line No. Rev Author Line
1 24 jeremybenn
#mach: crisv10
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#output: Basic clock cycles, total @: 3\n
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#output: Memory source stall cycles: 1\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#sim: --cris-cycles=basic
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 .include "testutils.inc"
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 startnostack
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 nop
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 move.d 0xff004567,r5
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 break 15

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