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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [raw15.ms] - Blame information for rev 33

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Line No. Rev Author Line
1 24 jeremybenn
; Checking read-after-write: cycles included in "all".
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#mach: crisv32
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#output: All accounted clock cycles, total @: 6\n
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#output: Memory source stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 2\n
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#output: Movem source stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#sim: --cris-cycles=all
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 .include "raw4.ms"

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