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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [x5-v32.ms] - Blame information for rev 33

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Line No. Rev Author Line
1 24 jeremybenn
#mach: crisv32
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#ld: --section-start=.text=0
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#sim: --cris-trace=basic
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#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n
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#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
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#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
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#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
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#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
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 .include "tmemv10.ms"

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