OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [m32r/] [bltz.cgs] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# m32r testcase for bltz $src2,$disp16
2
# mach(): m32r m32rx
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global bltz
9
bltz:
10
        mvi_h_gr r4, -1
11
        bltz r4, test0pass
12
test1fail:
13
        fail
14
 
15
test0pass:
16
        mvi_h_gr r4, 0
17
        bltz r4, test1fail
18
 
19
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.