OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh/] [pass.s] - Blame information for rev 325

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# sh testcase, pass
2
# mach:  all
3
# as(sh):       -defsym sim_cpu=0
4
# as(shdsp):    -defsym sim_cpu=1 -dsp
5
 
6
        .include "testutils.inc"
7
 
8
        start
9
        set_grs_a5a5
10
        test_grs_a5a5
11
        pass
12
 
13
        exit 0
14
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.