OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh64/] [media/] [andc.cgs] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
# sh testcase for andc $rm, $rn, $rd -*- Asm -*-
2 
# mach: all
3 
# as: -isa=shmedia
4 
# ld: -m shelf64
5 
 
6 
        .include "media/testutils.inc"
7 
 
8 
        start
9 
 
10 
init:
11 
        pta wrong, tr0
12 
 
13 
andc1:
14 
        # X . !X = 0.
15 
        movi 3, r0
16 
        movi 3, r1
17 
        andc r0, r1, r2
18 
        bnei r2, 0, tr0
19 
 
20 
andc2:
21 
        # X . 0 = X.
22 
        movi 3, r0
23 
        movi 0, r1
24 
        andc r0, r1, r2
25 
        bnei r2, 3, tr0
26 
 
27 
andc3:
28 
        # wide X . 0 = wide X.
29 
        movi 0x1020, r0
30 
        shlli r0, 8, r0
31 
        ori r0, 0x30, r0
32 
        shlli r0, 8, r0
33 
        ori r0, 0x40, r0
34 
        shlli r0, 8, r0
35 
        ori r0, 0x50, r0
36 
        shlli r0, 8, r0
37 
        ori r0, 0x60, r0
38 
        shlli r0, 8, r0
39 
        ori r0, 0x70, r0
40 
        shlli r0, 8, r0
41 
        ori r0, 0x80, r0
42 
        movi 0, r1
43 
        andc r0, r1, r2
44 
        bne r0, r2, tr0
45 
 
46 
okay:
47 
        pass
48 
 
49 
wrong:
50 
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.