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;; GCC machine description for IA-32 and x86-64.

;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,

;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010

;; Free Software Foundation, Inc.

;; Mostly by William Schelter.

;; x86_64 support added by Jan Hubicka

;;

;; This file is part of GCC.

;;

;; GCC is free software; you can redistribute it and/or modify

;; it under the terms of the GNU General Public License as published by

;; the Free Software Foundation; either version 3, or (at your option)

;; any later version.

;;

;; GCC is distributed in the hope that it will be useful,

;; but WITHOUT ANY WARRANTY; without even the implied warranty of

;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

;; GNU General Public License for more details.

;;

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING3.  If not see

;; .  */

;;

;; The original PO technology requires these to be ordered by speed,

;; so that assigner will pick the fastest.

;;

;; See file "rtl.def" for documentation on define_insn, match_*, et. al.

;;

;; The special asm out single letter directives following a '%' are:

;; L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.

;; C -- print opcode suffix for set/cmov insn.

;; c -- like C, but print reversed condition

;; E,e -- likewise, but for compare-and-branch fused insn.

;; F,f -- likewise, but for floating-point.

;; O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",

;;      otherwise nothing

;; R -- print the prefix for register names.

;; z -- print the opcode suffix for the size of the current operand.

;; Z -- likewise, with special suffixes for x87 instructions.

;; * -- print a star (in certain assembler syntax)

;; A -- print an absolute memory reference.

;; w -- print the operand as if it's a "word" (HImode) even if it isn't.

;; s -- print a shift double count, followed by the assemblers argument

;;      delimiter.

;; b -- print the QImode name of the register for the indicated operand.

;;      %b0 would print %al if operands[0] is reg 0.

;; w --  likewise, print the HImode name of the register.

;; k --  likewise, print the SImode name of the register.

;; q --  likewise, print the DImode name of the register.

;; x --  likewise, print the V4SFmode name of the register.

;; t --  likewise, print the V8SFmode name of the register.

;; h -- print the QImode name for a "high" register, either ah, bh, ch or dh.

;; y -- print "st(0)" instead of "st" as a register.

;; d -- print duplicated register operand for AVX instruction.

;; D -- print condition for SSE cmp instruction.

;; P -- if PIC, print an @PLT suffix.

;; X -- don't print any sort of PIC '@' suffix for a symbol.

;; & -- print some in-use local-dynamic symbol name.

;; H -- print a memory address offset by 8; used for sse high-parts

;; Y -- print condition for XOP pcom* instruction.

;; + -- print a branch hint as 'cs' or 'ds' prefix

;; ; -- print a semicolon (after prefixes due to bug in older gas).

;; UNSPEC usage:

(define_constants

  [; Relocation specifiers

   (UNSPEC_GOT                  0)

   (UNSPEC_GOTOFF               1)

   (UNSPEC_GOTPCREL             2)

   (UNSPEC_GOTTPOFF             3)

   (UNSPEC_TPOFF                4)

   (UNSPEC_NTPOFF               5)

   (UNSPEC_DTPOFF               6)

   (UNSPEC_GOTNTPOFF            7)

   (UNSPEC_INDNTPOFF            8)

   (UNSPEC_PLTOFF               9)

   (UNSPEC_MACHOPIC_OFFSET      10)

   ; Prologue support

   (UNSPEC_STACK_ALLOC          11)

   (UNSPEC_SET_GOT              12)

   (UNSPEC_SSE_PROLOGUE_SAVE    13)

   (UNSPEC_REG_SAVE             14)

   (UNSPEC_DEF_CFA              15)

   (UNSPEC_SET_RIP              16)

   (UNSPEC_SET_GOT_OFFSET       17)

   (UNSPEC_MEMORY_BLOCKAGE      18)

   ; TLS support

   (UNSPEC_TP                   20)

   (UNSPEC_TLS_GD               21)

   (UNSPEC_TLS_LD_BASE          22)

   (UNSPEC_TLSDESC              23)

   ; Other random patterns

   (UNSPEC_SCAS                 30)

   (UNSPEC_FNSTSW               31)

   (UNSPEC_SAHF                 32)

   (UNSPEC_PARITY               33)

   (UNSPEC_FSTCW                34)

   (UNSPEC_ADD_CARRY            35)

   (UNSPEC_FLDCW                36)

   (UNSPEC_REP                  37)

   (UNSPEC_LD_MPIC              38)     ; load_macho_picbase

   (UNSPEC_TRUNC_NOOP           39)

   ; For SSE/MMX support:

   (UNSPEC_FIX_NOTRUNC          40)

   (UNSPEC_MASKMOV              41)

   (UNSPEC_MOVMSK               42)

   (UNSPEC_MOVNT                43)

   (UNSPEC_MOVU                 44)

   (UNSPEC_RCP                  45)

   (UNSPEC_RSQRT                46)

   (UNSPEC_SFENCE               47)

   (UNSPEC_PFRCP                49)

   (UNSPEC_PFRCPIT1             40)

   (UNSPEC_PFRCPIT2             41)

   (UNSPEC_PFRSQRT              42)

   (UNSPEC_PFRSQIT1             43)

   (UNSPEC_MFENCE               44)

   (UNSPEC_LFENCE               45)

   (UNSPEC_PSADBW               46)

   (UNSPEC_LDDQU                47)

   (UNSPEC_MS_TO_SYSV_CALL      48)

   ; Generic math support

   (UNSPEC_COPYSIGN             50)

   (UNSPEC_IEEE_MIN             51)     ; not commutative

   (UNSPEC_IEEE_MAX             52)     ; not commutative

   ; x87 Floating point

   (UNSPEC_SIN                  60)

   (UNSPEC_COS                  61)

   (UNSPEC_FPATAN               62)

   (UNSPEC_FYL2X                63)

   (UNSPEC_FYL2XP1              64)

   (UNSPEC_FRNDINT              65)

   (UNSPEC_FIST                 66)

   (UNSPEC_F2XM1                67)

   (UNSPEC_TAN                  68)

   (UNSPEC_FXAM                 69)

   ; x87 Rounding

   (UNSPEC_FRNDINT_FLOOR        70)

   (UNSPEC_FRNDINT_CEIL         71)

   (UNSPEC_FRNDINT_TRUNC        72)

   (UNSPEC_FRNDINT_MASK_PM      73)

   (UNSPEC_FIST_FLOOR           74)

   (UNSPEC_FIST_CEIL            75)

   ; x87 Double output FP

   (UNSPEC_SINCOS_COS           80)

   (UNSPEC_SINCOS_SIN           81)

   (UNSPEC_XTRACT_FRACT         84)

   (UNSPEC_XTRACT_EXP           85)

   (UNSPEC_FSCALE_FRACT         86)

   (UNSPEC_FSCALE_EXP           87)

   (UNSPEC_FPREM_F              88)

   (UNSPEC_FPREM_U              89)

   (UNSPEC_FPREM1_F             90)

   (UNSPEC_FPREM1_U             91)

   (UNSPEC_C2_FLAG              95)

   (UNSPEC_FXAM_MEM             96)

   ; SSP patterns

   (UNSPEC_SP_SET               100)

   (UNSPEC_SP_TEST              101)

   (UNSPEC_SP_TLS_SET           102)

   (UNSPEC_SP_TLS_TEST          103)

   ; SSSE3

   (UNSPEC_PSHUFB               120)

   (UNSPEC_PSIGN                121)

   (UNSPEC_PALIGNR              122)

   ; For SSE4A support

   (UNSPEC_EXTRQI               130)

   (UNSPEC_EXTRQ                131)

   (UNSPEC_INSERTQI             132)

   (UNSPEC_INSERTQ              133)

   ; For SSE4.1 support

   (UNSPEC_BLENDV               134)

   (UNSPEC_INSERTPS             135)

   (UNSPEC_DP                   136)

   (UNSPEC_MOVNTDQA             137)

   (UNSPEC_MPSADBW              138)

   (UNSPEC_PHMINPOSUW           139)

   (UNSPEC_PTEST                140)

   (UNSPEC_ROUND                141)

   ; For SSE4.2 support

   (UNSPEC_CRC32                143)

   (UNSPEC_PCMPESTR             144)

   (UNSPEC_PCMPISTR             145)

   ; For FMA4 support

   (UNSPEC_FMA4_INTRINSIC       150)

   (UNSPEC_FMA4_FMADDSUB        151)

   (UNSPEC_FMA4_FMSUBADD        152)

   (UNSPEC_XOP_UNSIGNED_CMP     151)

   (UNSPEC_XOP_TRUEFALSE        152)

   (UNSPEC_XOP_PERMUTE          153)

   (UNSPEC_FRCZ                 154)

   ; For AES support

   (UNSPEC_AESENC               159)

   (UNSPEC_AESENCLAST           160)

   (UNSPEC_AESDEC               161)

   (UNSPEC_AESDECLAST           162)

   (UNSPEC_AESIMC               163)

   (UNSPEC_AESKEYGENASSIST      164)

   ; For PCLMUL support

   (UNSPEC_PCLMUL               165)

   ; For AVX support

   (UNSPEC_PCMP                 166)

   (UNSPEC_VPERMIL              167)

   (UNSPEC_VPERMIL2             168)

   (UNSPEC_VPERMIL2F128         169)

   (UNSPEC_MASKLOAD             170)

   (UNSPEC_MASKSTORE            171)

   (UNSPEC_CAST                 172)

   (UNSPEC_VTESTP               173)

  ])

(define_constants

  [(UNSPECV_BLOCKAGE            0)

   (UNSPECV_STACK_PROBE         1)

   (UNSPECV_EMMS                2)

   (UNSPECV_LDMXCSR             3)

   (UNSPECV_STMXCSR             4)

   (UNSPECV_FEMMS               5)

   (UNSPECV_CLFLUSH             6)

   (UNSPECV_ALIGN               7)

   (UNSPECV_MONITOR             8)

   (UNSPECV_MWAIT               9)

   (UNSPECV_CMPXCHG             10)

   (UNSPECV_XCHG                12)

   (UNSPECV_LOCK                13)

   (UNSPECV_PROLOGUE_USE        14)

   (UNSPECV_CLD                 15)

   (UNSPECV_VZEROALL            16)

   (UNSPECV_VZEROUPPER          17)

   (UNSPECV_RDTSC               18)

   (UNSPECV_RDTSCP              19)

   (UNSPECV_RDPMC               20)

   (UNSPECV_VSWAPMOV            21)

   (UNSPECV_LLWP_INTRINSIC      22)

   (UNSPECV_SLWP_INTRINSIC      23)

   (UNSPECV_LWPVAL_INTRINSIC    24)

   (UNSPECV_LWPINS_INTRINSIC    25)

  ])

;; Constants to represent pcomtrue/pcomfalse variants

(define_constants

  [(PCOM_FALSE                  0)

   (PCOM_TRUE                   1)

   (COM_FALSE_S                 2)

   (COM_FALSE_P                 3)

   (COM_TRUE_S                  4)

   (COM_TRUE_P                  5)

  ])

;; Constants used in the XOP pperm instruction

(define_constants

  [(PPERM_SRC                   0x00)   /* copy source */

   (PPERM_INVERT                0x20)   /* invert source */

   (PPERM_REVERSE               0x40)   /* bit reverse source */

   (PPERM_REV_INV               0x60)   /* bit reverse & invert src */

   (PPERM_ZERO                  0x80)   /* all 0's */

   (PPERM_ONES                  0xa0)   /* all 1's */

   (PPERM_SIGN                  0xc0)   /* propagate sign bit */

   (PPERM_INV_SIGN              0xe0)   /* invert & propagate sign */

   (PPERM_SRC1                  0x00)   /* use first source byte */

   (PPERM_SRC2                  0x10)   /* use second source byte */

   ])

;; Registers by name.

(define_constants

  [(AX_REG                       0)

   (DX_REG                       1)

   (CX_REG                       2)

   (BX_REG                       3)

   (SI_REG                       4)

   (DI_REG                       5)

   (BP_REG                       6)

   (SP_REG                       7)

   (ST0_REG                      8)

   (ST1_REG                      9)

   (ST2_REG                     10)

   (ST3_REG                     11)

   (ST4_REG                     12)

   (ST5_REG                     13)

   (ST6_REG                     14)

   (ST7_REG                     15)

   (FLAGS_REG                   17)

   (FPSR_REG                    18)

   (FPCR_REG                    19)

   (XMM0_REG                    21)

   (XMM1_REG                    22)

   (XMM2_REG                    23)

   (XMM3_REG                    24)

   (XMM4_REG                    25)

   (XMM5_REG                    26)

   (XMM6_REG                    27)

   (XMM7_REG                    28)

   (MM0_REG                     29)

   (MM1_REG                     30)

   (MM2_REG                     31)

   (MM3_REG                     32)

   (MM4_REG                     33)

   (MM5_REG                     34)

   (MM6_REG                     35)

   (MM7_REG                     36)

   (R8_REG                      37)

   (R9_REG                      38)

   (R10_REG                     39)

   (R11_REG                     40)

   (R12_REG                     41)

   (R13_REG                     42)

   (XMM8_REG                    45)

   (XMM9_REG                    46)

   (XMM10_REG                   47)

   (XMM11_REG                   48)

   (XMM12_REG                   49)

   (XMM13_REG                   50)

   (XMM14_REG                   51)

   (XMM15_REG                   52)

  ])

;; Insns whose names begin with "x86_" are emitted by gen_FOO calls

;; from i386.c.

;; In C guard expressions, put expressions which may be compile-time

;; constants first.  This allows for better optimization.  For

;; example, write "TARGET_64BIT && reload_completed", not

;; "reload_completed && TARGET_64BIT".

;; Processor type.

(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,

                    generic64,amdfam10"

  (const (symbol_ref "ix86_schedule")))

;; A basic instruction type.  Refinements due to arguments to be

;; provided in other attributes.

(define_attr "type"

  "other,multi,

   alu,alu1,negnot,imov,imovx,lea,

   incdec,ishift,ishift1,rotate,rotate1,imul,idiv,

   icmp,test,ibr,setcc,icmov,

   push,pop,call,callv,leave,

   str,bitmanip,

   fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,

   sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,

   sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,

   ssemuladd,sse4arg,lwp,

   mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"

  (const_string "other"))

;; Main data type used by the insn

(define_attr "mode"

  "unknown,none,QI,HI,SI,DI,TI,OI,SF,DF,XF,TF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF"

  (const_string "unknown"))

;; The CPU unit operations uses.

(define_attr "unit" "integer,i387,sse,mmx,unknown"

  (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")

           (const_string "i387")

         (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,

                          sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,

                          ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg")

           (const_string "sse")

         (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")

           (const_string "mmx")

         (eq_attr "type" "other")

           (const_string "unknown")]

         (const_string "integer")))

;; The (bounding maximum) length of an instruction immediate.

(define_attr "length_immediate" ""

  (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,

                          bitmanip")

           (const_int 0)

         (eq_attr "unit" "i387,sse,mmx")

           (const_int 0)

         (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,

                          imul,icmp,push,pop")

           (symbol_ref "ix86_attr_length_immediate_default(insn,1)")

         (eq_attr "type" "imov,test")

           (symbol_ref "ix86_attr_length_immediate_default(insn,0)")

         (eq_attr "type" "call")

           (if_then_else (match_operand 0 "constant_call_address_operand" "")

             (const_int 4)

             (const_int 0))

         (eq_attr "type" "callv")

           (if_then_else (match_operand 1 "constant_call_address_operand" "")

             (const_int 4)

             (const_int 0))

         ;; We don't know the size before shorten_branches.  Expect

         ;; the instruction to fit for better scheduling.

         (eq_attr "type" "ibr")

           (const_int 1)

         ]

         (symbol_ref "/* Update immediate_length and other attributes! */

                      gcc_unreachable (),1")))

;; The (bounding maximum) length of an instruction address.

(define_attr "length_address" ""

  (cond [(eq_attr "type" "str,other,multi,fxch")

           (const_int 0)

         (and (eq_attr "type" "call")

              (match_operand 0 "constant_call_address_operand" ""))

             (const_int 0)

         (and (eq_attr "type" "callv")

              (match_operand 1 "constant_call_address_operand" ""))

             (const_int 0)

         ]

         (symbol_ref "ix86_attr_length_address_default (insn)")))

;; Set when length prefix is used.

(define_attr "prefix_data16" ""

  (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")

           (const_int 0)

         (eq_attr "mode" "HI")

           (const_int 1)

         (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))

           (const_int 1)

        ]

        (const_int 0)))

;; Set when string REP prefix is used.

(define_attr "prefix_rep" ""

  (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")

           (const_int 0)

         (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))

           (const_int 1)

        ]

        (const_int 0)))

;; Set when 0f opcode prefix is used.

(define_attr "prefix_0f" ""

  (if_then_else

    (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")

         (eq_attr "unit" "sse,mmx"))

    (const_int 1)

    (const_int 0)))

;; Set when REX opcode prefix is used.

(define_attr "prefix_rex" ""

  (cond [(ne (symbol_ref "!TARGET_64BIT") (const_int 0))

           (const_int 0)

         (and (eq_attr "mode" "DI")

              (and (eq_attr "type" "!push,pop,call,callv,leave,ibr")

                   (eq_attr "unit" "!mmx")))

           (const_int 1)

         (and (eq_attr "mode" "QI")

              (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")

                  (const_int 0)))

           (const_int 1)

         (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")

             (const_int 0))

           (const_int 1)

         (and (eq_attr "type" "imovx")

              (match_operand:QI 1 "ext_QIreg_operand" ""))

           (const_int 1)

        ]

        (const_int 0)))

;; There are also additional prefixes in 3DNOW, SSSE3.

;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,

;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.

;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.

(define_attr "prefix_extra" ""

  (cond [(eq_attr "type" "ssemuladd,sse4arg")

           (const_int 2)

         (eq_attr "type" "sseiadd1,ssecvt1")

           (const_int 1)

        ]

        (const_int 0)))

;; Prefix used: original, VEX or maybe VEX.

(define_attr "prefix" "orig,vex,maybe_vex"

  (if_then_else (eq_attr "mode" "OI,V8SF,V4DF")

    (const_string "vex")

    (const_string "orig")))

;; VEX W bit is used.

(define_attr "prefix_vex_w" "" (const_int 0))

;; The length of VEX prefix

;; Only instructions with 0f prefix can have 2 byte VEX prefix,

;; 0f38/0f3a prefixes can't.  In i386.md 0f3[8a] is

;; still prefix_0f 1, with prefix_extra 1.

(define_attr "length_vex" ""

  (if_then_else (and (eq_attr "prefix_0f" "1")

                     (eq_attr "prefix_extra" "0"))

    (if_then_else (eq_attr "prefix_vex_w" "1")

      (symbol_ref "ix86_attr_length_vex_default (insn, 1, 1)")

      (symbol_ref "ix86_attr_length_vex_default (insn, 1, 0)"))

    (if_then_else (eq_attr "prefix_vex_w" "1")

      (symbol_ref "ix86_attr_length_vex_default (insn, 0, 1)")

      (symbol_ref "ix86_attr_length_vex_default (insn, 0, 0)"))))

;; Set when modrm byte is used.

(define_attr "modrm" ""

  (cond [(eq_attr "type" "str,leave")

           (const_int 0)

         (eq_attr "unit" "i387")

           (const_int 0)

         (and (eq_attr "type" "incdec")

              (and (eq (symbol_ref "TARGET_64BIT") (const_int 0))

                   (ior (match_operand:SI 1 "register_operand" "")

                        (match_operand:HI 1 "register_operand" ""))))

           (const_int 0)

         (and (eq_attr "type" "push")

              (not (match_operand 1 "memory_operand" "")))

           (const_int 0)

         (and (eq_attr "type" "pop")

              (not (match_operand 0 "memory_operand" "")))

           (const_int 0)

         (and (eq_attr "type" "imov")

              (and (not (eq_attr "mode" "DI"))

                   (ior (and (match_operand 0 "register_operand" "")

                             (match_operand 1 "immediate_operand" ""))

                        (ior (and (match_operand 0 "ax_reg_operand" "")

                                  (match_operand 1 "memory_displacement_only_operand" ""))

                             (and (match_operand 0 "memory_displacement_only_operand" "")

                                  (match_operand 1 "ax_reg_operand" ""))))))

           (const_int 0)

         (and (eq_attr "type" "call")

              (match_operand 0 "constant_call_address_operand" ""))

             (const_int 0)

         (and (eq_attr "type" "callv")

              (match_operand 1 "constant_call_address_operand" ""))

             (const_int 0)

         (and (eq_attr "type" "alu,alu1,icmp,test")

              (match_operand 0 "ax_reg_operand" ""))

             (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))")

         ]

         (const_int 1)))

;; The (bounding maximum) length of an instruction in bytes.

;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.

;; Later we may want to split them and compute proper length as for

;; other insns.

(define_attr "length" ""

  (cond [(eq_attr "type" "other,multi,fistp,frndint")

           (const_int 16)

         (eq_attr "type" "fcmp")

           (const_int 4)

         (eq_attr "unit" "i387")

           (plus (const_int 2)

                 (plus (attr "prefix_data16")

                       (attr "length_address")))

         (ior (eq_attr "prefix" "vex")

              (and (eq_attr "prefix" "maybe_vex")

                    (ne (symbol_ref "TARGET_AVX") (const_int 0))))

           (plus (attr "length_vex")

                 (plus (attr "length_immediate")

                       (plus (attr "modrm")

                             (attr "length_address"))))]

         (plus (plus (attr "modrm")

                     (plus (attr "prefix_0f")

                           (plus (attr "prefix_rex")

                                 (plus (attr "prefix_extra")

                                       (const_int 1)))))

               (plus (attr "prefix_rep")

                     (plus (attr "prefix_data16")

                           (plus (attr "length_immediate")

                                 (attr "length_address")))))))

;; The `memory' attribute is `none' if no memory is referenced, `load' or

;; `store' if there is a simple memory reference therein, or `unknown'

;; if the instruction is complex.

(define_attr "memory" "none,load,store,both,unknown"

  (cond [(eq_attr "type" "other,multi,str,lwp")

           (const_string "unknown")

         (eq_attr "type" "lea,fcmov,fpspc")

           (const_string "none")

         (eq_attr "type" "fistp,leave")

           (const_string "both")

         (eq_attr "type" "frndint")

           (const_string "load")

         (eq_attr "type" "push")

           (if_then_else (match_operand 1 "memory_operand" "")

             (const_string "both")

             (const_string "store"))

         (eq_attr "type" "pop")

           (if_then_else (match_operand 0 "memory_operand" "")

             (const_string "both")

             (const_string "load"))

         (eq_attr "type" "setcc")

           (if_then_else (match_operand 0 "memory_operand" "")

             (const_string "store")

             (const_string "none"))

         (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")

           (if_then_else (ior (match_operand 0 "memory_operand" "")

                              (match_operand 1 "memory_operand" ""))

             (const_string "load")

             (const_string "none"))

         (eq_attr "type" "ibr")

           (if_then_else (match_operand 0 "memory_operand" "")

             (const_string "load")

             (const_string "none"))

         (eq_attr "type" "call")

           (if_then_else (match_operand 0 "constant_call_address_operand" "")

             (const_string "none")

             (const_string "load"))

         (eq_attr "type" "callv")

           (if_then_else (match_operand 1 "constant_call_address_operand" "")

             (const_string "none")

             (const_string "load"))

         (and (eq_attr "type" "alu1,negnot,ishift1,sselog1")

              (match_operand 1 "memory_operand" ""))

           (const_string "both")

         (and (match_operand 0 "memory_operand" "")

              (match_operand 1 "memory_operand" ""))

           (const_string "both")

         (match_operand 0 "memory_operand" "")

           (const_string "store")

         (match_operand 1 "memory_operand" "")

           (const_string "load")

         (and (eq_attr "type"

                 "!alu1,negnot,ishift1,

                   imov,imovx,icmp,test,bitmanip,

                   fmov,fcmp,fsgn,

                   sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1,

                   sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt")

              (match_operand 2 "memory_operand" ""))

           (const_string "load")

         (and (eq_attr "type" "icmov,ssemuladd,sse4arg")

              (match_operand 3 "memory_operand" ""))

           (const_string "load")

        ]

        (const_string "none")))

;; Indicates if an instruction has both an immediate and a displacement.

(define_attr "imm_disp" "false,true,unknown"

  (cond [(eq_attr "type" "other,multi")

           (const_string "unknown")

         (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")

              (and (match_operand 0 "memory_displacement_operand" "")

                   (match_operand 1 "immediate_operand" "")))

           (const_string "true")

         (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")

              (and (match_operand 0 "memory_displacement_operand" "")

                   (match_operand 2 "immediate_operand" "")))

           (const_string "true")

        ]

        (const_string "false")))

;; Indicates if an FP operation has an integer source.

(define_attr "fp_int_src" "false,true"

  (const_string "false"))

;; Defines rounding mode of an FP operation.

(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"

  (const_string "any"))

;; Define attribute to classify add/sub insns that consumes carry flag (CF)

(define_attr "use_carry" "0,1" (const_string "0"))

;; Define attribute to indicate unaligned ssemov insns

(define_attr "movu" "0,1" (const_string "0"))

;; Describe a user's asm statement.

(define_asm_attributes

  [(set_attr "length" "128")

   (set_attr "type" "multi")])

;; All integer comparison codes.

(define_code_iterator int_cond [ne eq ge gt le lt geu gtu leu ltu])

;; All floating-point comparison codes.

(define_code_iterator fp_cond [unordered ordered

                               uneq unge ungt unle unlt ltgt])

(define_code_iterator plusminus [plus minus])

(define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus])

;; Base name for define_insn

(define_code_attr plusminus_insn

  [(plus "add") (ss_plus "ssadd") (us_plus "usadd")

   (minus "sub") (ss_minus "sssub") (us_minus "ussub")])

;; Base name for insn mnemonic.

(define_code_attr plusminus_mnemonic

  [(plus "add") (ss_plus "adds") (us_plus "addus")

   (minus "sub") (ss_minus "subs") (us_minus "subus")])

(define_code_attr plusminus_carry_mnemonic

  [(plus "adc") (minus "sbb")])

;; Mark commutative operators as such in constraints.

(define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%")

                        (minus "") (ss_minus "") (us_minus "")])

;; Mapping of signed max and min

(define_code_iterator smaxmin [smax smin])

;; Mapping of unsigned max and min

(define_code_iterator umaxmin [umax umin])

;; Mapping of signed/unsigned max and min

(define_code_iterator maxmin [smax smin umax umin])

;; Base name for integer and FP insn mnemonic

(define_code_attr maxminiprefix [(smax "maxs") (smin "mins")

                                 (umax "maxu") (umin "minu")])

(define_code_attr maxminfprefix [(smax "max") (smin "min")])

;; Mapping of logic operators

(define_code_iterator any_logic [and ior xor])

(define_code_iterator any_or [ior xor])

;; Base name for insn mnemonic.

(define_code_attr logicprefix [(and "and") (ior "or") (xor "xor")])

;; Mapping of abs neg operators

(define_code_iterator absneg [abs neg])

;; Base name for x87 insn mnemonic.

(define_code_attr absnegprefix [(abs "abs") (neg "chs")])

;; Used in signed and unsigned widening multiplications.

(define_code_iterator any_extend [sign_extend zero_extend])

;; Various insn prefixes for signed and unsigned operations.

(define_code_attr u [(sign_extend "") (zero_extend "u")

                     (div "") (udiv "u")])

(define_code_attr s [(sign_extend "s") (zero_extend "u")])

;; Used in signed and unsigned divisions.

(define_code_iterator any_div [div udiv])

;; Instruction prefix for signed and unsigned operations.

(define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")

                             (div "i") (udiv "")])

;; All single word integer modes.

(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])

;; Single word integer modes without DImode.

(define_mode_iterator SWI124 [QI HI SI])

;; Single word integer modes without QImode.

(define_mode_iterator SWI248 [HI SI (DI "TARGET_64BIT")])

;; Single word integer modes without QImode and HImode.

(define_mode_iterator SWI48 [SI (DI "TARGET_64BIT")])

;; All math-dependant single and double word integer modes.

(define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")

                             (HI "TARGET_HIMODE_MATH")

                             SI DI (TI "TARGET_64BIT")])

;; Math-dependant single word integer modes.

(define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")

                            (HI "TARGET_HIMODE_MATH")

                            SI (DI "TARGET_64BIT")])

;; Math-dependant single word integer modes without QImode.

(define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")

                               SI (DI "TARGET_64BIT")])

;; Half mode for double word integer modes.

(define_mode_iterator DWIH [(SI "!TARGET_64BIT")

                            (DI "TARGET_64BIT")])

;; Double word integer modes.

(define_mode_attr DWI [(SI "DI") (DI "TI")])

(define_mode_attr dwi [(SI "di") (DI "ti")])

;; Instruction suffix for integer modes.

(define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])

;; Register class for integer modes.

(define_mode_attr r [(QI "q") (HI "r") (SI "r") (DI "r")])

;; Immediate operand constraint for integer modes.

(define_mode_attr i [(QI "n") (HI "n") (SI "i") (DI "e")])

;; General operand constraint for word modes.

(define_mode_attr g [(QI "qmn") (HI "rmn") (SI "g") (DI "rme")])

;; Immediate operand constraint for double integer modes.

(define_mode_attr di [(SI "iF") (DI "e")])

;; General operand predicate for integer modes.

(define_mode_attr general_operand

        [(QI "general_operand")

         (HI "general_operand")

         (SI "general_operand")

         (DI "x86_64_general_operand")

         (TI "x86_64_general_operand")])

;; General sign/zero extend operand predicate for integer modes.

(define_mode_attr general_szext_operand

        [(QI "general_operand")

         (HI "general_operand")

         (SI "general_operand")

         (DI "x86_64_szext_general_operand")])

;; SSE and x87 SFmode and DFmode floating point modes

(define_mode_iterator MODEF [SF DF])

;; All x87 floating point modes

(define_mode_iterator X87MODEF [SF DF XF])

;; All integer modes handled by x87 fisttp operator.

(define_mode_iterator X87MODEI [HI SI DI])

;; All integer modes handled by integer x87 operators.

(define_mode_iterator X87MODEI12 [HI SI])

;; All integer modes handled by SSE cvtts?2si* operators.

(define_mode_iterator SSEMODEI24 [SI DI])

;; SSE asm suffix for floating point modes

(define_mode_attr ssemodefsuffix [(SF "s") (DF "d")])

;; SSE vector mode corresponding to a scalar mode

(define_mode_attr ssevecmode

  [(QI "V16QI") (HI "V8HI") (SI "V4SI") (DI "V2DI") (SF "V4SF") (DF "V2DF")])

;; Instruction suffix for REX 64bit operators.

(define_mode_attr rex64suffix [(SI "") (DI "{q}")])

;; This mode iterator allows :P to be used for patterns that operate on

;; pointer-sized quantities.  Exactly one of the two alternatives will match.

(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])

;; Scheduling descriptions

(include "pentium.md")

(include "ppro.md")

(include "k6.md")

(include "athlon.md")

(include "geode.md")

(include "atom.md")

;; Operand and operator predicates and constraints

(include "predicates.md")

(include "constraints.md")

;; Compare and branch/compare and store instructions.

(define_expand "cbranch4"

  [(set (reg:CC FLAGS_REG)

        (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand" "")

                    (match_operand:SDWIM 2 "" "")))

   (set (pc) (if_then_else

               (match_operator 0 "comparison_operator"

                [(reg:CC FLAGS_REG) (const_int 0)])

               (label_ref (match_operand 3 "" ""))

               (pc)))]

  ""

{

  if (MEM_P (operands[1]) && MEM_P (operands[2]))

    operands[1] = force_reg (mode, operands[1]);

  ix86_compare_op0 = operands[1];

  ix86_compare_op1 = operands[2];

  ix86_expand_branch (GET_CODE (operands[0]), operands[3]);

  DONE;

})

(define_expand "cstore4"

  [(set (reg:CC FLAGS_REG)

        (compare:CC (match_operand:SWIM 2 "nonimmediate_operand" "")

                    (match_operand:SWIM 3 "" "")))

   (set (match_operand:QI 0 "register_operand" "")

        (match_operator 1 "comparison_operator"

          [(reg:CC FLAGS_REG) (const_int 0)]))]

  ""

{

  if (MEM_P (operands[2]) && MEM_P (operands[3]))

    operands[2] = force_reg (mode, operands[2]);

  ix86_compare_op0 = operands[2];

  ix86_compare_op1 = operands[3];

  ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);

  DONE;

})

(define_expand "cmp_1"

  [(set (reg:CC FLAGS_REG)

        (compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "")

                    (match_operand:SWI48 1 "" "")))]

  ""

  "")

(define_insn "*cmp_ccno_1"

  [(set (reg FLAGS_REG)

        (compare (match_operand:SWI 0 "nonimmediate_operand" ",?m")

                 (match_operand:SWI 1 "const0_operand" "")))]

  "ix86_match_ccmode (insn, CCNOmode)"

  "@

   test{}\t%0, %0

   cmp{}\t{%1, %0|%0, %1}"

  [(set_attr "type" "test,icmp")

   (set_attr "length_immediate" "0,1")

   (set_attr "mode" "")])

(define_insn "*cmp_1"

  [(set (reg FLAGS_REG)

        (compare (match_operand:SWI 0 "nonimmediate_operand" "m,")

                 (match_operand:SWI 1 "" ",m")))]

  "ix86_match_ccmode (insn, CCmode)"

  "cmp{}\t{%1, %0|%0, %1}"

  [(set_attr "type" "icmp")

   (set_attr "mode" "")])

(define_insn "*cmp_minus_1"

  [(set (reg FLAGS_REG)

        (compare

          (minus:SWI (match_operand:SWI 0 "nonimmediate_operand" "m,")

                     (match_operand:SWI 1 "" ",m"))

          (const_int 0)))]

  "ix86_match_ccmode (insn, CCGOCmode)"

  "cmp{}\t{%1, %0|%0, %1}"

  [(set_attr "type" "icmp")

   (set_attr "mode" "")])