OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [g++.dg/] [eh/] [simd-1.C] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 301 jeremybenn
// Test EH when V2SI SIMD registers are involved.
2
// Contributed by Aldy Hernandez (aldy@quesejoda.com).
3
// { dg-options "-O -Wno-abi" }
4
// { dg-options "-O -w" { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
5
// { dg-do run }
6
 
7
typedef int __attribute__((vector_size (8))) vecint;
8
 
9
vecint vecfunc (vecint beachbum)
10
{
11
  return beachbum;
12
}
13
 
14
void f3 (void)
15
{
16
  /* Force a use of a V2SI register if available.  On the PPC/E500,
17
     this will cause the compiler to save the registers in this
18
     function in 64-bits.  */
19
  vecint foobar = (vecint) {0, 0};
20
  foobar = vecfunc (foobar);
21
 
22
  throw int();
23
}
24
 
25
void f2 (void)
26
{
27
  vecint foobar = (vecint) {0, 0};
28
  foobar = vecfunc (foobar);
29
 
30
  f3 ();
31
}
32
 
33
void f1 (void)
34
{
35
  int i;
36
  try
37
    {
38
      f2 ();
39
    }
40
  catch (int)
41
    {
42
      i = 9;
43
    }
44
}
45
 
46
int main ()
47
{
48
  f1 ();
49
  return 0;
50
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.