OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20040730-1.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 297 jeremybenn
/*  PR tree-opt/16827
2
    This used to ICE in tree-ssa-loop-im.c */
3
 
4
extern unsigned short dev_roles[];
5
void super_1_sync(int *rdev2)
6
{
7
 int i;
8
 int max_dev = 0;
9
 
10
 for (i =0;i<20;i++)
11
  if (rdev2[i] > max_dev)
12
   max_dev = rdev2[i];
13
 
14
 for (i=0; i<max_dev;i++)
15
  dev_roles[max_dev] = 0xfffe;
16
 
17
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.