OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.dg/] [vect/] [vect-3.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* { dg-require-effective-target vect_int } */
2
/* { dg-require-effective-target vect_float } */
3
 
4
#include <stdarg.h>
5
#include "tree-vect.h"
6
 
7
#define N 20
8
 
9
float a[N];
10
float e[N];
11
float b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
12
float c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
13
float d[N] = {0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30};
14
int ic[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
15
int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
16
int ia[N];
17
 
18
__attribute__ ((noinline)) int
19
main1 ()
20
{
21
  int i;
22
 
23
  for (i = 0; i < N; i++)
24
    {
25
      a[i] = b[i] + c[i] + d[i];
26
      e[i] = b[i] + c[i] + d[i];
27
      ia[i] = ib[i] + ic[i];
28
    }
29
 
30
  /* check results:  */
31
  for (i = 0; i <N; i++)
32
    {
33
      float fres = b[i] + c[i] + d[i];
34
      int ires = ib[i] + ic[i];
35
      if (a[i] != fres || e[i] != fres || ia[i] != ires)
36
        abort ();
37
    }
38
 
39
  return 0;
40
}
41
 
42
int main (void)
43
{
44
  check_vect ();
45
 
46
  return main1 ();
47
}
48
 
49
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
50
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
51
/* { dg-final { cleanup-tree-dump "vect" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.