OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [asm.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 jeremybenn
/* ARM and Thumb asm statements should be able to access the constant
2
   pool.  */
3
/* { dg-do compile } */
4
extern unsigned x[];
5
unsigned *trapTable()
6
{
7
  unsigned *i;
8
 
9
  __asm__ volatile("ldr %0,%1" : "=r"(i) : "m"(x[0]));
10
 
11
  return i;
12
}
13
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.