OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vst3_lanef32.c] - Blame information for rev 313

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 jeremybenn
/* Test the `vst3_lanef32' ARM Neon intrinsic.  */
2
/* This file was autogenerated by neon-testgen.  */
3
 
4
/* { dg-do assemble } */
5
/* { dg-require-effective-target arm_neon_ok } */
6
/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
7
 
8
#include "arm_neon.h"
9
 
10
void test_vst3_lanef32 (void)
11
{
12
  float32_t *arg0_float32_t;
13
  float32x2x3_t arg1_float32x2x3_t;
14
 
15
  vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
16
}
17
 
18
/* { dg-final { scan-assembler "vst3\.32\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
19
/* { dg-final { cleanup-saved-temps } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.