OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [pr43698.c] - Blame information for rev 313

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 jeremybenn
/* { dg-do run } */
2
/* { dg-options "-Os -march=armv7-a" } */
3
#include <stdint.h>
4
#include <stdlib.h>
5
 
6
 
7
char do_reverse_endian = 0;
8
 
9
#  define bswap_32(x) \
10
  ((((x) & 0xff000000) >> 24) | \
11
   (((x) & 0x00ff0000) >>  8) | \
12
   (((x) & 0x0000ff00) <<  8) | \
13
   (((x) & 0x000000ff) << 24))
14
 
15
#define EGET(X) \
16
  (__extension__ ({ \
17
      uint64_t __res; \
18
      if (!do_reverse_endian) {    __res = (X); \
19
      } else if (sizeof(X) == 4) { __res = bswap_32((X)); \
20
      } \
21
      __res; \
22
    }))
23
 
24
void __attribute__((noinline)) X(char **phdr, char **data, int *phoff)
25
{
26
  *phdr = *data + EGET(*phoff);
27
}
28
 
29
int main()
30
{
31
  char *phdr;
32
  char *data = (char *)0x40164000;
33
  int phoff = 0x34;
34
  X(&phdr, &data, &phoff);
35
  if (phdr != (char *)0x40164034)
36
    abort ();
37
  exit (0);
38
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.