URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [abi-2.c] - Blame information for rev 338

Details | Compare with Previous | View Log


/* Make certain that we pass __m256i in the correct register for AVX.  */
/* { dg-do compile } */
/* { dg-options "-O1 -mavx" } */
/* { dg-options "-mabi=sysv -O1 -mavx" { target x86_64-*-mingw* } } */
 
typedef long long __m256i __attribute__ ((__vector_size__ (32)));
__m256i foo (void) { return (__m256i){ 1, 2, 3, 4 }; }
 
/* { dg-final { scan-assembler-times "ymm0" 1 } } */

Line No.	Rev	Author	Line
1	318	jeremybenn	`/* Make certain that we pass __m256i in the correct register for AVX. */`
2			`/* { dg-do compile } */`
3			`/* { dg-options "-O1 -mavx" } */`
4			`/* { dg-options "-mabi=sysv -O1 -mavx" { target x86_64--mingw } } */`
5
6			`typedef long long __m256i __attribute__ ((__vector_size__ (32)));`
7			`__m256i foo (void) { return (__m256i){ 1, 2, 3, 4 }; }`
8
9			`/* { dg-final { scan-assembler-times "ymm0" 1 } } */`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [abi-2.c] - Blame information for rev 338