OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [isa-6.c] - Blame information for rev 779

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do run } */
2
/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */
3
/* { dg-options "-march=amdfam10 -mno-sse4" } */
4
 
5
extern void abort (void);
6
 
7
int
8
main ()
9
{
10
#if !defined __SSE__
11
  abort ();
12
#endif
13
#if !defined __SSE2__
14
  abort ();
15
#endif
16
#if !defined __SSE3__
17
  abort ();
18
#endif
19
#if defined __SSSE3__
20
  abort ();
21
#endif
22
#if defined __SSE4_1__
23
  abort ();
24
#endif
25
#if defined __SSE4_2__
26
  abort ();
27
#endif
28
#if !defined __SSE4A__
29
  abort ();
30
#endif
31
#if defined __AVX__
32
  abort ();
33
#endif
34
#if defined __FMA4__
35
  abort ();
36
#endif
37
  return 0;
38
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.