OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr34012.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* PR rtl-optimization/34012 */
2
/* { dg-do compile } */
3
/* { dg-require-effective-target lp64 } */
4
/* { dg-options "-O2" } */
5
 
6
void bar (long int *);
7
void
8
foo (void)
9
{
10
  long int buf[10];
11
  buf[0] = 0x0808080808080808;
12
  buf[1] = 0x0808080808080808;
13
  buf[2] = 0x0808080808080808;
14
  buf[3] = 0x0808080808080808;
15
  buf[4] = 0x0808080808080808;
16
  buf[5] = 0x0808080808080808;
17
  buf[6] = 0x0808080808080808;
18
  buf[7] = 0x0808080808080808;
19
  buf[8] = 0x0808080808080808;
20
  buf[9] = 0x0808080808080808;
21
  bar (buf);
22
}
23
 
24
/* Check that CSE did its job and fwprop hasn't undone it.  */
25
/* { dg-final { scan-assembler-times "578721382704613384|0808080808080808" 1 } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.